mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCK

Useful for testing stuff in C_ENVIRONMENT_BOOTBLOCK, like
VBOOT with separate verstage.

Changes:
* Use symbols to set up CAR and STACK
* Zero CAR area
* Move BIST failure checking to cpu folder
* Rename functions where necessary

Tested:
* qemu-2.11.2 machine pc
* qemu-2.11.2 machine q35

Test result:
* BIST error reporting is still working.
* Console starts in bootblock
* SeaBios 1.11.2 as payload is still working

Change-Id: Ibf341002c36d868b9b44c8b37381fa78ae5c4381
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

4 files changed, 42 insertions, 22 deletions

diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig
index 10b5a936c4..4394530fad 100644
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select MAINBOARD_HAS_NATIVE_VGA_INIT
 	select MAINBOARD_FORCE_NATIVE_VGA_INIT
+	select BOOTBLOCK_CONSOLE
 
 config MAINBOARD_DIR
 	string
@@ -28,17 +29,24 @@ config MMCONF_BASE_ADDRESS
 	hex
 	default 0xb0000000
 
+# Skip the first 64KiB as coreboot table pointer is installed
+# at address 0
 config DCACHE_RAM_BASE
 	hex
-	default 0xd0000
+	default 0x10000
 
+# Memory at 0xa0000 decodes to VGA
 config DCACHE_RAM_SIZE
 	hex
-	default 0x10000
+	default 0x90000
 
 # Do not show IFD/blob options since QEMU doesn't care
 config HAVE_INTEL_FIRMWARE
 	bool
 	default n
 
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x4000
+
 endif # BOARD_EMULATION_QEMU_X86_Q35
diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc
index 923a28ed34..1503220c9c 100644
--- a/src/mainboard/emulation/qemu-q35/Makefile.inc
+++ b/src/mainboard/emulation/qemu-q35/Makefile.inc
@@ -1,5 +1,5 @@
-cpu_incs-y += $(src)/mainboard/emulation/qemu-i440fx/cache_as_ram.inc
 ramstage-y += ../qemu-i440fx/northbridge.c
 ramstage-y += ../qemu-i440fx/memory.c
 ramstage-y += ../qemu-i440fx/fw_cfg.c
 romstage-y += ../qemu-i440fx/memory.c
+bootblock-y += bootblock.c
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index 3625cf903a..2125bd1db3 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -12,6 +12,8 @@
  */
 
 #include <arch/io.h>
+#include <bootblock_common.h>
+#include <southbridge/intel/i82801ix/i82801ix.h>
 
 /* Just define these here, there is no gm35.h file to include. */
 #define D0F0_PCIEXBAR_LO 0x60
@@ -39,7 +41,29 @@ static void bootblock_northbridge_init(void)
 	pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg);
 }
 
-static void bootblock_mainboard_init(void)
+static void enable_spi_prefetch(void)
+{
+	u8 reg8;
+	pci_devfn_t dev;
+
+	dev = PCI_DEV(0, 0x1f, 0);
+
+	reg8 = pci_read_config8(dev, 0xdc);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void bootblock_southbridge_init(void)
+{
+	enable_spi_prefetch();
+
+	/* Enable RCBA */
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), D31F0_RCBA,
+			(uintptr_t)DEFAULT_RCBA | 1);
+}
+
+void bootblock_soc_init(void)
 {
 	bootblock_northbridge_init();
 	bootblock_southbridge_init();
diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c
index deb94af777..2b8d9351c0 100644
--- a/src/mainboard/emulation/qemu-q35/romstage.c
+++ b/src/mainboard/emulation/qemu-q35/romstage.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2004 Stefan Reinauer
+ * Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -16,32 +17,19 @@
 #include <stdint.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <timestamp.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-
+#include <southbridge/intel/i82801ix/i82801ix.h>
+#include <program_loading.h>
 
-void * asmlinkage romstage_main(unsigned long bist)
+asmlinkage void car_stage_entry(void)
 {
-	int cbmem_was_initted;
-
-	/* init_timer(); */
-	post_code(0x05);
-
 	i82801ix_early_init();
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	cbmem_was_initted = !cbmem_recovery(0);
+	cbmem_recovery(0);
 
-	timestamp_init(timestamp_get());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
-	/* Emulation uses fixed low stack during ramstage. */
-	return NULL;
+	run_ramstage();
 }