diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2023-07-04 09:22:39 +0300 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-06 13:54:45 +0000 |
commit | 6aaa4f9198666b28f6081458f4d5184167305f99 (patch) | |
tree | 62993d2b60a1d1529d02329f1541bda26d9351dd /src/mainboard/emulation/qemu-q35 | |
parent | cde4f3b2790d52ef38106c7ba91eea5d53e03a93 (diff) |
emulation/qemu-q35: Enable ECAM earlier
Align implementation with real hardwares, such that ECAM
(PCI configuration via MMIO) is available for use when
console is initialised.
Change-Id: I288991f31d3f1678132aa4315168c09eabbbe98d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76206
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/emulation/qemu-q35')
-rw-r--r-- | src/mainboard/emulation/qemu-q35/bootblock.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index bacdae8685..d40ff0f98d 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -7,7 +7,7 @@ #include "q35.h" -static void bootblock_northbridge_init(void) +void bootblock_soc_early_init(void) { /* * The "io" variant of the config access is explicitly used to @@ -24,9 +24,6 @@ static void bootblock_northbridge_init(void) const uint32_t pciexbar = make_pciexbar(); pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_HI, 0); pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, pciexbar); - - if (CONFIG(BOOTBLOCK_CONSOLE)) - mainboard_machine_check(); } static void bootblock_southbridge_init(void) @@ -40,6 +37,8 @@ static void bootblock_southbridge_init(void) void bootblock_soc_init(void) { - bootblock_northbridge_init(); + if (CONFIG(BOOTBLOCK_CONSOLE)) + mainboard_machine_check(); + bootblock_southbridge_init(); } |