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authorArthur Heymans <arthur@aheymans.xyz>2020-12-01 18:29:13 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-03-18 08:10:11 +0000
commite69d2dfdb70c33dfcc07a54c217601f498c2214c (patch)
treefa79b9a46e7c80b6c5ac06ec582b79db66c56d4a /src/mainboard/emulation/qemu-q35/memmap.c
parentff485f2bcef9d0c8cf9536f6b8bc87edbe718e04 (diff)
mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP init
Tested with and without -enable-kvm, with -smp 1 2 and 32. Change-Id: I612cebcd2ddef809434eb9bfae9d8681cda112ef Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48262 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/qemu-q35/memmap.c')
-rw-r--r--src/mainboard/emulation/qemu-q35/memmap.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/emulation/qemu-q35/memmap.c b/src/mainboard/emulation/qemu-q35/memmap.c
index f3ce42c485..5c4292138d 100644
--- a/src/mainboard/emulation/qemu-q35/memmap.c
+++ b/src/mainboard/emulation/qemu-q35/memmap.c
@@ -8,6 +8,7 @@
#include <device/pci_ops.h>
#include <mainboard/emulation/qemu-i440fx/memory.h>
#include <mainboard/emulation/qemu-i440fx/fw_cfg.h>
+#include <cpu/intel/smm_reloc.h>
#include "q35.h"
@@ -35,6 +36,16 @@ void mainboard_machine_check(void)
/* QEMU-specific register */
#define EXT_TSEG_MBYTES 0x50
+#define SMRAMC 0x9d
+#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
+#define G_SMRAME (1 << 3)
+#define D_LCK (1 << 4)
+#define D_CLS (1 << 5)
+#define D_OPEN (1 << 6)
+#define ESMRAMC 0x9e
+#define T_EN (1 << 0)
+#define TSEG_SZ_MASK (3 << 1)
+#define H_SMRAME (1 << 7)
void smm_region(uintptr_t *start, size_t *size)
{
@@ -57,3 +68,16 @@ void smm_region(uintptr_t *start, size_t *size)
*start = qemu_get_memory_size() * KiB - *size;
printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB);
}
+
+void smm_lock(void)
+{
+ /*
+ * LOCK the SMM memory window and enable normal SMM.
+ * After running this function, only a full reset can
+ * make the SMM registers writable again.
+ */
+ printk(BIOS_DEBUG, "Locking SMM.\n");
+
+ pci_or_config8(PCI_DEV(0, 0, 0), ESMRAMC, T_EN);
+ pci_write_config8(PCI_DEV(0, 0, 0), SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG);
+}