aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/emulation/qemu-q35/mainboard.c
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-03 08:06:32 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-26 07:15:19 +0200
commitb9646a2bdc1c29961a326fc7f657433067d53ff0 (patch)
treed2376fa3ed948422cadc940235d28118ac62188d /src/mainboard/emulation/qemu-q35/mainboard.c
parentaad0747216cab56a8cee5c1401c094543ed8be2d (diff)
emulation/qemu-q35: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO in qemu-q35 emulation To enable MMIO style access, add (move) explicit PCI IO config write in the bootblock. As there is no northbridge/x/x/bootblock.c file, a mainboard/x/x/bootblock.c file is added for this purpose. Change-Id: I979efb3d9b2f359a9ccbd1b4f6c05f83bab43007 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3599 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-q35/mainboard.c')
-rw-r--r--src/mainboard/emulation/qemu-q35/mainboard.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c
index 3740064a80..78c92a9b38 100644
--- a/src/mainboard/emulation/qemu-q35/mainboard.c
+++ b/src/mainboard/emulation/qemu-q35/mainboard.c
@@ -27,7 +27,6 @@
#include <console/console.h>
#define Q35_PAM0 0x90
-#define Q35_PCIEXBAR_ADDR 0xb0000000
static const unsigned char qemu_q35_irqs[] = {
10, 10, 11, 11,
@@ -59,9 +58,6 @@ static void qemu_nb_init(device_t dev)
/* setup IRQ routing southbridge devices */
for (i = 25; i < 32; i++)
pci_assign_irqs(0, i, qemu_q35_irqs);
-
- /* setup mmconfig */
- pci_write_config32(dev, 0x60, Q35_PCIEXBAR_ADDR | 1);
}
static void qemu_nb_read_resources(struct device *dev)
@@ -69,7 +65,7 @@ static void qemu_nb_read_resources(struct device *dev)
pci_dev_read_resources(dev);
/* reserve mmconfig */
- fixed_mem_resource(dev, 2, Q35_PCIEXBAR_ADDR >> 10, 0x10000000 >> 10,
+ fixed_mem_resource(dev, 2, CONFIG_MMCONF_BASE_ADDRESS >> 10, 0x10000000 >> 10,
IORESOURCE_RESERVE);
}