diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-07-30 17:46:17 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-14 19:06:25 +0200 |
| commit | 8ab989e31561cea0c6af5d5e242dd2be97bc73b4 (patch) | |
| tree | 31bc3a2175762b179d2fc093c34f62c18b15b9ee /src/mainboard/emulation/qemu-i440fx/northbridge.c | |
| parent | 589ef9de8faa2db11a7ce2769fc1d9396a82886b (diff) | |
src/mainboard: Capitalize ROM, RAM, CPU and APIC
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/emulation/qemu-i440fx/northbridge.c')
| -rw-r--r-- | src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 26cbda5a6b..575069cc7e 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -72,7 +72,7 @@ static void cpu_pci_domain_read_resources(struct device *dev) fw_cfg_load_file("etc/e820", list); for (i = 0; i < size/sizeof(*list); i++) { switch (list[i].type) { - case 1: /* ram */ + case 1: /* RAM */ printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n", list[i].address, list[i].length); if (list[i].address == 0) { @@ -135,7 +135,7 @@ static void cpu_pci_domain_read_resources(struct device *dev) * Reserve the region between top-of-ram and the * mmconf xbar (ar 0xb0000000), so coreboot doesn't * place pci bars there. The region isn't declared as - * pci io window in the acpi tables (\_SB.PCI0._CRS). + * pci io window in the ACPI tables (\_SB.PCI0._CRS). */ res = new_resource(dev, idx++); res->base = tomk * 1024; |