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authorArthur Heymans <arthur@aheymans.xyz>2023-06-20 12:08:33 +0200
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2023-06-22 21:04:31 +0000
commite3929efd1e328280e36c4b14a4a1b7e26b259836 (patch)
treed0650ce00fc296968ee4a7591e6bdbbfeab9d6ea /src/mainboard/emulation/qemu-aarch64/include
parent58fe703e088be0af934cc0bf31fc60f87fcfde76 (diff)
mb/qemu/aarch64: Add PCI support
Run with "-device pci-bridge,chassis_nr=1" argument to add a bridge and see that it gets found and picked up by the resource allocator. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iad5d87731066a4009d2c4930a01bc15543d9447a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75925 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/emulation/qemu-aarch64/include')
-rw-r--r--src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
index 50dd35ebdc..70acac8519 100644
--- a/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
+++ b/src/mainboard/emulation/qemu-aarch64/include/mainboard/addressmap.h
@@ -28,3 +28,20 @@
#define VIRT_MMIO_BASE 0x0a000000
#define VIRT_PLATFORM_BUS_BASE 0x0c000000
#define VIRT_SECRAM_BASE 0xe000000
+#define VIRT_PCIE_LOW_MMIO_BASE 0x10000000
+#define VIRT_PCIE_LOW_MMIO_LIMIT 0x3efeffff
+/*
+ * From hw/arm/virt.c:
+ * Highmem IO Regions: This memory map is floating, located after the RAM.
+ * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
+ * top of the RAM, so that its base get the same alignment as the size,
+ * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
+ * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
+ * Note the extended_memmap is sized so that it eventually also includes the
+ * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
+ * index of base_memmap).
+ */
+#define VIRT_PCIE_ECAM_BASE 0x4010000000 /* The one in lower memory does not seem to work */
+#define VIRT_PCIE_ECAM_SIZE (256 * MiB)
+#define VIRT_PCIE_HIGH_MMIO_BASE 0x8000000000ULL
+#define VIRT_PCIE_HIGH_MMIO_LIMIT 0xffffffffffULL