- First pass at getting the powerpc ports to compile

  The static device tree is not built properly at all yet, but at least we get through it.
  FIXME (What is the proper way to handle add in boards?)
- Add generic div64 support and ppc div64 support
- Fix abuild so it properly generates the CC line when cross compiling.
- Add one more possible ppc cross compiler target


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 108 insertions, 2 deletions

diff --git a/src/mainboard/embeddedplanet/ep405pc/Config.lb b/src/mainboard/embeddedplanet/ep405pc/Config.lb
index 4b76162e17..9f071bf621 100644
--- a/src/mainboard/embeddedplanet/ep405pc/Config.lb
+++ b/src/mainboard/embeddedplanet/ep405pc/Config.lb
@@ -9,12 +9,12 @@ initobject init.c
 driver pci_bridge.c
 
 arch ppc end
-cpu ppc/ppc4xx end
+chip cpu/ppc/ppc4xx device pnp 0.0 on end end
 
 ##
 ## Include the secondary Configuration files 
 ##
-southbridge winbond/w83c553 end
+chip southbridge/winbond/w83c553 device pnp 0.0 on end end
 
 ##
 ## Build the objects we have code for in this directory.
diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb
index 9acea4955f..d37db77dc2 100644
--- a/src/mainboard/embeddedplanet/ep405pc/Options.lb
+++ b/src/mainboard/embeddedplanet/ep405pc/Options.lb
@@ -8,6 +8,41 @@ uses ISA_IO_BASE
 uses ISA_MEM_BASE 
 uses TTYS0_BASE 
 uses _IO_BASE 
+
+uses CPU_OPT
+uses CROSS_COMPILE 
+uses HAVE_OPTION_TABLE
+uses CONFIG_COMPRESS 
+uses CONFIG_CHIP_CONFIGURE
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_USE_INIT
+uses CONFIG_CONSOLE_SERIAL8250 
+uses TTYS0_BAUD TTYS0_DIV
+uses NO_POST
+uses CONFIG_IDE
+uses CONFIG_FS_STREAM
+uses CONFIG_FS_EXT2
+uses CONFIG_FS_ISO9660
+uses CONFIG_FS_FAT
+uses AUTOBOOT_CMDLINE
+uses CONFIG_SYS_CLK_FREQ
+uses IDE_BOOT_DRIVE
+#uses IDE_SWAB
+uses IDE_OFFSET 
+uses ROM_SIZE
+uses _RESET
+uses _EXCEPTION_VECTORS
+uses _ROMBASE
+uses _ROMSTART
+uses _RAMBASE
+#uses _RAMSTART
+uses EMBEDDED_RAM_SIZE
+uses STACK_SIZE HEAP_SIZE
+
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
@@ -33,3 +68,74 @@ default _IO_BASE=ISA_IO_BASE
 ##
 default TTYS0_BASE=0xef600300-ISA_IO_BASE
 
+## Enable PPC405 instructions
+default CPU_OPT="-Wa,-m405"
+default CPU_OPT=""
+
+## Use stage 1 initialization code
+default CONFIG_USE_INIT=1
+
+## Use chip configuration
+default CONFIG_CHIP_CONFIGURE=1
+
+## We don't use compressed image
+default CONFIG_COMPRESS=0
+
+## Turn off POST codes
+default NO_POST=1
+
+## Enable serial console
+default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_CONSOLE_SERIAL8250=1
+# Divisor of 69 == 9600 baud due to weird clocking
+default TTYS0_DIV=69
+default TTYS0_BAUD=9600
+
+## Boot linux from IDE
+default CONFIG_IDE=1
+default CONFIG_FS_STREAM=1
+default CONFIG_FS_EXT2=1
+default CONFIG_FS_ISO9660=1
+default CONFIG_FS_FAT=1
+default AUTOBOOT_CMDLINE="hda1:/vmlinuz"
+
+default ROM_SIZE=1048576
+
+## Board has fixed size RAM
+default EMBEDDED_RAM_SIZE=64*1024*1024
+
+## LinuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+
+##
+## Use a 64K stack
+##
+default STACK_SIZE=0x10000
+
+##
+## Use a 64K heap
+##
+default HEAP_SIZE=0x10000
+
+##
+## System clock
+##
+default CONFIG_SYS_CLK_FREQ=33
+
+##
+default _ROMBASE=0xfff00000
+
+## Reset vector address
+default _RESET=0xfffffffc
+
+## Exception vectors
+default _EXCEPTION_VECTORS=_ROMBASE+0x100
+
+## linuxBIOS ROM start address
+default _ROMSTART=0xfff03000
+
+## linuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+
+### End Options.lb
+end