diff options
| author | Eric Biederman <ebiederm@xmission.com> | 2004-11-05 10:48:04 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2004-11-05 10:48:04 +0000 |
| commit | 709850a21b1bdfb0018aa2a7ee06a7407bbd465c (patch) | |
| tree | 9aa0549858c03180139a7d528e5cb21982eff1ba /src/mainboard/embeddedplanet/ep405pc/Options.lb | |
| parent | d0805e0b55e63957b3641fa70cf1db624389e3f6 (diff) | |
- Ensure every copy of Options.lb uses:
CROSS_COMPILE
CC
HOSTCC
OBJCOPY
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/embeddedplanet/ep405pc/Options.lb')
| -rw-r--r-- | src/mainboard/embeddedplanet/ep405pc/Options.lb | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb new file mode 100644 index 0000000000..9acea4955f --- /dev/null +++ b/src/mainboard/embeddedplanet/ep405pc/Options.lb @@ -0,0 +1,35 @@ +## +## Config file for the Embedded Planet EP405PC Computing Engine +## + +uses PCIC0_CFGADDR +uses PCIC0_CFGDATA +uses ISA_IO_BASE +uses ISA_MEM_BASE +uses TTYS0_BASE +uses _IO_BASE +uses CROSS_COMPILE +uses CC +uses HOSTCC +uses OBJCOPY + +## +## Set PCI configuration register addresses +## +default PCIC0_CFGADDR=0xeec00000 +default PCIC0_CFGDATA=0xeec00004 + +## +## Set PCI/ISA I/O and memory base address +## +default ISA_IO_BASE=0xe8000000 +default ISA_MEM_BASE=0x80000000 +default _IO_BASE=ISA_IO_BASE + +## +## HACK ALERT: the UART0 registers are not in the PCI I/O address space +## but both IDE and UART use the same routines for I/O (inb/outb). To get +## around this we set TTYSO_BASE to the difference between the two. +## +default TTYS0_BASE=0xef600300-ISA_IO_BASE + |