summaryrefslogtreecommitdiff
path: root/src/mainboard/ecs
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2017-11-23 13:58:34 +0530
committerSubrata Banik <subrata.banik@intel.com>2017-12-02 03:20:15 +0000
commit0baad61a4e2f66f91d18578a7260db19a3531caa (patch)
treeb636360c79b7a4795a422b857e8e2fc439ff82fd /src/mainboard/ecs
parent2153ea5b83461547c854b2cd784b1638a3feeb31 (diff)
soc/intel/cannonlake: Initialize PMC controller
PMC controller gets hidden during FSP-Silicon initialization using sideband interface on CannonLake platform. Hence accessing PWRMBASE using PCI config space will return invalid BAR value as 0xFFFFF000. Also PMC PCI driver will not be able to initialize PMC controller as its not showing over PCI bus. coreboot PCI enumeration log shows: PCI: Static device PCI: 00:1f.2 not found, disabling it. This patch ensures PMC controller is getting initialized using boot state machine right after FSP Silicon Init returns (BS_DEV_INIT_CHIPS/ BS_ON_EXIT). TEST=Ensures PWRMBASE address is 0xFE000000 and PMC controller is getting initialized during BS_DEV_INIT_CHIPES/BS_ON_EXIT. Change-Id: Ife7389f0f035b66837aace89d6e6b866e494cbe4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/ecs')
0 files changed, 0 insertions, 0 deletions