amd/geode_lx: Remove most boards

There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.

Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 0 insertions, 321 deletions

diff --git a/src/mainboard/digitallogic/Kconfig b/src/mainboard/digitallogic/Kconfig
deleted file mode 100644
index 9b08501dde..0000000000
--- a/src/mainboard/digitallogic/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_DIGITALLOGIC
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/digitallogic/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/digitallogic/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	string
-	default "DIGITAL-LOGIC"
-
-endif # VENDOR_DIGITALLOGIC
diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig b/src/mainboard/digitallogic/msm800sev/Kconfig
deleted file mode 100644
index bc8e3ac71b..0000000000
--- a/src/mainboard/digitallogic/msm800sev/Kconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-if BOARD_DIGITALLOGIC_MSM800SEV
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_GEODE_LX
-	select NORTHBRIDGE_AMD_LX
-	select SOUTHBRIDGE_AMD_CS5536
-	select SUPERIO_WINBOND_W83627HF
-	select HAVE_PIRQ_TABLE
-	select PIRQ_ROUTE
-	select UDELAY_TSC
-	select BOARD_ROMSIZE_KB_256
-	select POWER_BUTTON_FORCE_ENABLE
-
-config MAINBOARD_DIR
-	string
-	default digitallogic/msm800sev
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "MSM800SEV"
-
-config IRQ_SLOT_COUNT
-	int
-	default 9
-
-endif # BOARD_DIGITALLOGIC_MSM800SEV
diff --git a/src/mainboard/digitallogic/msm800sev/Kconfig.name b/src/mainboard/digitallogic/msm800sev/Kconfig.name
deleted file mode 100644
index 0f3dad03cf..0000000000
--- a/src/mainboard/digitallogic/msm800sev/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_DIGITALLOGIC_MSM800SEV
-	bool "MSM800SEV"
diff --git a/src/mainboard/digitallogic/msm800sev/board_info.txt b/src/mainboard/digitallogic/msm800sev/board_info.txt
deleted file mode 100644
index 21476adbd2..0000000000
--- a/src/mainboard/digitallogic/msm800sev/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: half
-Board URL: http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV
diff --git a/src/mainboard/digitallogic/msm800sev/cmos.layout b/src/mainboard/digitallogic/msm800sev/cmos.layout
deleted file mode 100644
index b238a379d8..0000000000
--- a/src/mainboard/digitallogic/msm800sev/cmos.layout
+++ /dev/null
@@ -1,28 +0,0 @@
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-456          1       e       1        ECC_memory
-1008         16      h       0        check_sum
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb
deleted file mode 100644
index b03d4c532c..0000000000
--- a/src/mainboard/digitallogic/msm800sev/devicetree.cb
+++ /dev/null
@@ -1,85 +0,0 @@
-chip northbridge/amd/lx
-	device domain 0 on
-		device pci 1.0 on end
-		device pci 1.1 on end
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
-			# How to get these? Boot linux and do this:
-			# rdmsr 0x51400025
-			register "lpc_serirq_enable" = "0x0000105a"
-			# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
-			register "lpc_serirq_polarity" = "0x0000EFA5"
-			# mode is high 10 bits (determined from code)
-			register "lpc_serirq_mode" = "1"
-			# Don't yet know how to find this.
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci f.0 on	# ISA Bridge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off #  Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.1 off #  Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.2 on #  Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on #  Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.5 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					device pnp 2e.6 off #  CIR
-						io 0x60 = 0x100
-					end
-					device pnp 2e.7 off #  GAME_MIDI_GIPO1
-						io 0x60 = 0x220
-						io 0x62 = 0x300
-						irq 0x70 = 9
-					end
-					device pnp 2e.8 off end #  GPIO2
-					device pnp 2e.9 off end #  GPIO3
-					device pnp 2e.a off end #  ACPI
-					device pnp 2e.b on #  HW Monitor
-						io 0x60 = 0x290
-						irq 0x70 = 5
-					end
-				end
-			end
-			device pci f.1 on end	# Flash controller
-			device pci f.2 on end	# IDE controller
-			device pci f.3 on end	# Audio
-			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-		end
-	end
-
-	# APIC cluster is late CPU init.
-	device cpu_cluster 0 on
-		chip cpu/amd/geode_lx
-			device lapic 0 on end
-		end
-	end
-
-end
diff --git a/src/mainboard/digitallogic/msm800sev/irq_tables.c b/src/mainboard/digitallogic/msm800sev/irq_tables.c
deleted file mode 100644
index 362cb2ae80..0000000000
--- a/src/mainboard/digitallogic/msm800sev/irq_tables.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pirq_routing.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 11
-#define PIRQB 5
-#define PIRQC 10
-#define PIRQD 10
-
-/* Map */
-#define M_PIRQA (1 << PIRQA)  /* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB)  /* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC)  /* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD)  /* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA  1 /* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB  2 /* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC  3 /* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD  4 /* Means Slot INTx# Connects To Chipset INTD# */
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* There can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x0f << 3)|0x0,   /* Where the interrupt router lies (dev) */
-	0,		 /* IRQs devoted exclusively to PCI usage */
-	0x100b,		 /* Vendor */
-	0x2b,		 /* Device */
-	0,		 /* Miniport data */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xe,		 /* u8 checksum. This has to be set to some
-			    value that would give 0 after the sum of all
-			    bytes for this structure (including checksum) */
-	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01 << 3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x0f << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x0, 0x0},
-		{0x00,(0x13 << 3)|0x0, {{0x01, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x12 << 3)|0x0, {{0x03, 0x0400}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x11 << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
-		{0x00,(0x0a << 3)|0x0, {{0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x00800}}, 0x1, 0x0},
-		{0x00,(0x0b << 3)|0x0, {{0x02, 0x0800}, {0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x00400}}, 0x2, 0x0},
-		{0x00,(0x0c << 3)|0x0, {{0x03, 0x0400}, {0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x00800}}, 0x3, 0x0},
-		{0x00,(0x0d << 3)|0x0, {{0x04, 0x0800}, {0x01, 0x0400}, {0x02, 0x0800}, {0x03, 0x00400}}, 0x4, 0x0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
deleted file mode 100644
index 82d3a36370..0000000000
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/lxdef.h>
-#include <southbridge/amd/cs5536/cs5536.h>
-#include <spd.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627hf/w83627hf.h>
-#include <northbridge/amd/lx/raminit.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-int spd_read_byte(unsigned device, unsigned address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-void asmlinkage mainboard_romstage_entry(unsigned long bist)
-{
-
-	static const struct mem_controller memctrl [] = {
-		{.channel0 = {DIMM0, DIMM1}}
-	};
-
-	SystemPreInit();
-	msr_init();
-
-	cs5536_early_setup();
-
-	/* NOTE: must do this AFTER the early_setup!
-	 * it is counting on some early MSR setup
-	 * for cs5536
-	 */
-	cs5536_disable_internal_uart();
-	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	pll_reset();
-
-	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
-	sdram_initialize(1, memctrl);
-
-	/* Switch from Cache as RAM to real RAM */
-	/* There are two ways we could think about this.
-	 1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code.
-		Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be.
-	 2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc.
-		That means we care about what is in the stack. If we are smart we set the CAR stack to the same location
-		as the rest of coreboot. If that is the case we can just do a wbinvd. The stack will be written into real
-		RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than
-		where LB would like it, you need to write some code to do a copy from cache to RAM
-
-	 We use method 1 on Norwich.
-	*/
-	post_code(0x02);
-	__asm__("wbinvd\n");
-	printk(BIOS_ERR, "Past wbinvd\n");
-	/* we are finding the return does not work on this board. Explicitly call the label that is
-	 * after the call to us. This is gross, but sometimes at this level it is the only way out
-	 */
-	done_cache_as_ram_main();
-}