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authorBruce Griffith <Bruce.Griffith@se-eng.com>2014-08-10 17:09:15 -0600
committerBruce Griffith <Bruce.Griffith@se-eng.com>2014-08-30 19:14:16 +0200
commit1a59039c24cfe5c74a805064d3a360709ad16526 (patch)
tree7860975252e93b6fe4dc7091b47ea5f16e9413ff /src/mainboard/cubietech/cubieboard
parentb266c6b5448b17647946eb926b07920c28524a55 (diff)
AMD Steppe Eagle: New integrated southbridge (Avalon)
00730F01 contains the Avalon southbridge and a Platform Security Processor (PSP). Supporting the PSP requires specific binaries to be included in the ROM. The fletcher utility is used to sign PSP binaries. The IMC access routines are not accessible for newer AMD parts that use pre-compiled AGESA. Change the Hudson code such that the IMC code is not compiled if IMC is not selected in Kconfig. Disable compilation of resume.c if HAVE_ACPI_RESUME is disabled. The newer AMD mainboards will initially be released without ACPI resume support (S3) due to the use of AGESA internals in the existing Hudson routines. The Makefile change allows newer mainboards to avoid the API issues. Change Kconfig such that the FWM flag is always set for PSP-enabled parts. This has the side effect of forcing the generation of the FWM directory in the absence of GEC, IMC, and xHCI. Change-Id: I6d056f54b60a64300841599490b9fafd561c4a7d Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6677 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Zheng Bao <zheng.bao@amd.com>
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