mb/clevo/kbl-u: Move memory init config to variant level

Memory init config is board specific. Thus, move it to variant level and
hook up variant romstage.c.

Change-Id: Id78788815ad9c4ed64f0172fb746ff6e50d608ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

1 files changed, 38 insertions, 0 deletions

diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c
new file mode 100644
index 0000000000..4e9d57c21a
--- /dev/null
+++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+#include <spd_bin.h>
+#include <string.h>
+#include <variant/romstage.h>
+
+static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+	const u16 RcompResistor[3] = {121, 81, 100};
+	memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+	const u16 RcompTarget[5] = {100, 40, 20, 20, 26};
+	memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+}
+
+void variant_configure_fspm(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+
+	struct spd_block blk = {
+		.addr_map = {0x50, 0x52},
+	};
+
+	get_spd_smbus(&blk);
+	dump_spd_info(&blk);
+
+	mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+	mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+	mem_cfg->DqPinsInterleaved = TRUE;
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+}