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authorFelix Singer <felixsinger@posteo.net>2020-12-06 04:58:23 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-12-08 20:49:44 +0000
commit8271cce95915d4f6d496d684c2654235bef55e62 (patch)
tree062112ab10a41f922d6e448b567846ff66425f94 /src/mainboard/clevo/cml-u
parente9da62a05fe8922f204c2f651c8345f8123f39c5 (diff)
mb/clevo/l140cu: Remove unnecessary device declarations
Remove unnecessary device declarations and remove comments where SMBIOS slot descriptions are used. Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48373 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/clevo/cml-u')
-rw-r--r--src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
index b7745a3d74..5b03f4c608 100644
--- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
+++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
@@ -141,7 +141,7 @@ chip soc/intel/cannonlake
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on # PCI Express Port 8
chip drivers/wifi/generic
- device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
+ device pci 00.0 on end
end
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
@@ -151,7 +151,6 @@ chip soc/intel/cannonlake
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end
device pci 1d.0 on # PCI Express Port 9
- device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[4]" = "8"
@@ -163,7 +162,6 @@ chip soc/intel/cannonlake
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on # PCI Express Port 13
- device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"