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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-27 17:55:22 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-29 06:01:34 +0000 |
| commit | 8e60571f6e751547a10a9db42817be404278bd01 (patch) | |
| tree | 4538c2ab7d7695bd87612575c527b619b4655563 /src/mainboard/clevo/cml-u/variants | |
| parent | c88a4794c8d7336495785ab2d55e219caf5173a9 (diff) | |
mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader
PcieRpSlotImplemented should only be set to 1 for PCIe ports
implementing a PCIe slot. Drop it for the on-board card reader.
Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/clevo/cml-u/variants')
| -rw-r--r-- | src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 55c5c6ebf8..e079dffff9 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -138,7 +138,6 @@ chip soc/intel/cannonlake register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" - register "PcieRpSlotImplemented[5]" = "1" end device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 |