diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-08-03 22:10:05 +0200 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-12 21:52:12 +0000 |
| commit | 8f7f4bf87a238dd046a376804b9e53162092f601 (patch) | |
| tree | 2c31aa38216a8fa376c8203a5435eda08138704f /src/mainboard/cavium | |
| parent | 6cf0e4a3536750cb1cd9ecec56463731db647fe5 (diff) | |
soc/amd/cezanne,common: factor out CPPC code to common AMD SoC code
The Cezanne CPPC ACPI table generation code also applies to Sabrina, so
move it to the common AMD SoC code directory so that it can be used for
Sabrina too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ce082a27429948f8af7f55944a1062ba03155da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66400
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/cavium')
0 files changed, 0 insertions, 0 deletions