diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-07-06 14:18:42 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-17 13:42:56 +0000 |
| commit | e836a43713c87c450ccb820188b6f81901ab9d24 (patch) | |
| tree | dc24c098ec2727df8bd3dafa063b1eff0681850d /src/mainboard/cavium | |
| parent | 870cbb91edd8578b0880aa2c2fc63bc29250b0d3 (diff) | |
mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(906a0h) silicon
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is
enableda on the system.
BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon
if not updated.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a1f60fda7575212bb694fc423bd229452515903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/cavium')
0 files changed, 0 insertions, 0 deletions