cavium: Add CN81xx SoC and eval board support

This adds Cavium CN81xx SoC and SFF EVB files.

Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK

BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs

romstage:
- Use minimal DRAM init only

devicetree:
- Convert FTD to static C file containing key value pairs

Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)

Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init

Not working:
- Booting a payload
- Booting upstream ATF

TODO:
- Configuration straps

Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

1 files changed, 24 insertions, 0 deletions

diff --git a/src/mainboard/cavium/cn8100_sff_evb/board.fmd b/src/mainboard/cavium/cn8100_sff_evb/board.fmd
new file mode 100644
index 0000000000..19987274ff
--- /dev/null
+++ b/src/mainboard/cavium/cn8100_sff_evb/board.fmd
@@ -0,0 +1,24 @@
+FLASH@0x0 8M {
+	WP_RO@0x0 0x400000 {
+		RO_SECTION@0x0 0x200000 {
+			# bootblock includes trusted/non-trusted CLIB, CSIB,
+			# and BL1FWs packaged in
+			# src/soc/cavium/common/Makefile.inc.
+			BOOTBLOCK@0x10000 0x70000
+			FMAP@0x90000 0x1000
+			COREBOOT(CBFS)@0x100000 0x100000
+		}
+	}
+	RW_SECTION_A@0x400000 0xe8000 {
+		VBLOCK_A@0x0 0x2000
+		FW_MAIN_A(CBFS)@0x2000 0xe5f00
+		RW_FWID_A@0xe7f00 0x100
+	}
+	RW_UNUSED@0x4e8000 0x8000
+	RW_ELOG@0x5d8000 0x1000
+	RW_SHARED@0x5e0000 0x10000 {
+		SHARED_DATA@0x0 0x10000
+	}
+	RW_NVRAM@0x5f0000 0x10000
+	CONSOLE@0x700000 0x100000
+}