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authorFelix Held <felix-coreboot@felixheld.de>2023-03-03 18:29:15 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-06 17:19:52 +0000
commitf773e12795b64d11920d8710d40f63e5791cf230 (patch)
treedf0963a616bb3455261c293fc45bc51d7b4e05e9 /src/mainboard/cavium/Kconfig
parent949bce5adf377bf82734e98d74ff3896f08003cd (diff)
soc/amd/picasso/include/southbridge: drop PM_CPU_CTRL define
Picasso and newer don't implement the P_CNT register to control the CPU duty cycle and also trap the C state control IO addresses directly in the CPU, so those won't reach the FCH. This register is unused in the Picasso code and not even defined any more in the Cezanne PPR. The Picasso PPR does define this register, but since it's useless and might even just be a leftover form a pre-Zen CPU generation, drop the define. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3820db542c4714a100c7d36de673daa1a06e4a67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/mainboard/cavium/Kconfig')
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