mb/bytedance: Add 2 SPR sockets server board bd_egs

Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids
Scalable Processor chipset.

It's utilising:
- 2 SPR sockets
- Max 32 DIMMs
- 33x CPU PCIe slots
- AST2600 for VGA and BMC remote management

Test:
  The board boots to Linux 5.10 with all 192 cores available.
  All PCIe devices and DIMMS are working.

  # sudo dmesg --level alert,crit,err,warn
  [ 46.636896] netlink: 'consul': attribute type 1 has an invalid length.

Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d
Co-authored-by: Jinfeng Li <lijinfeng01@ieisystem.com>
Co-authored-by: Long Cao <caolong01@inspur.com>
Co-authored-by: Hao Wang <wanghao11@inspur.com>
Co-authored-by: Chenyu Lan <lanchenyu@inspur.com>
Co-authored-by: Lay Kong <lay.kong@intel.com>
Co-authored-by: Kehong Chen <kehong.chen@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Dong Wei <weidong.wd@bytedance.com>
Co-authored-by: Chenchen Li <lichenchen.carl@bytedance.com>
Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com>
Reviewed-by: Haitao Nie <niehaitao@bytedance.com>
Reviewed-by: Shijian Ge <geshijian@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

14 files changed, 740 insertions, 0 deletions

diff --git a/src/mainboard/bytedance/bd_egs/Kconfig b/src/mainboard/bytedance/bd_egs/Kconfig
new file mode 100644
index 0000000000..c83177fe41
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/Kconfig
@@ -0,0 +1,31 @@
+if BOARD_BYTEDANCE_BD_EGS
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_65536
+	select MAINBOARD_USES_FSP2_0
+	select SOC_INTEL_SAPPHIRERAPIDS_SP
+	select SUPERIO_ASPEED_AST2400
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select IPMI_KCS
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_HAS_TPM2
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
+
+config MAINBOARD_DIR
+	default "bytedance/bd_egs"
+
+config MAINBOARD_PART_NUMBER
+	default "ByteDance bd_egs"
+
+config MAINBOARD_FAMILY
+	default "Intel Eagle Stream Server"
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
+config MAX_SOCKET
+	default 2
+
+endif
diff --git a/src/mainboard/bytedance/bd_egs/Kconfig.name b/src/mainboard/bytedance/bd_egs/Kconfig.name
new file mode 100644
index 0000000000..170ec2d5e5
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_BYTEDANCE_BD_EGS
+	bool "ByteDance bd_egs"
diff --git a/src/mainboard/bytedance/bd_egs/Makefile.inc b/src/mainboard/bytedance/bd_egs/Makefile.inc
new file mode 100644
index 0000000000..e6e739e4e1
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/Makefile.inc
@@ -0,0 +1,4 @@
+bootblock-y += bootblock.c gpio.c
+romstage-y += romstage.c
+ramstage-y += ramstage.c gpio.c
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
diff --git a/src/mainboard/bytedance/bd_egs/acpi/platform.asl b/src/mainboard/bytedance/bd_egs/acpi/platform.asl
new file mode 100644
index 0000000000..4853874f8c
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/acpi/platform.asl
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Enable ACPI _SWS methods */
+#include <soc/intel/common/acpi/acpi_wake_source.asl>
+#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+/* Port 80 POST */
+OperationRegion (DBG0, SystemIO, 0x80, 0x02)
+Field (DBG0, ByteAcc, Lock, Preserve)
+{
+	IO80, 8,
+	IO81, 8
+}
+
+/*
+ * The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method (_PTS, 1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method (_WAK, 1)
+{
+	Return (Package (){ 0, 0 })
+}
diff --git a/src/mainboard/bytedance/bd_egs/board.fmd b/src/mainboard/bytedance/bd_egs/board.fmd
new file mode 100644
index 0000000000..1a58bb196b
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/board.fmd
@@ -0,0 +1,13 @@
+FLASH@0xfc000000 64M {
+	SI_ALL@0x0 0x03000000 {
+		SI_DESC@0x0 0x1000
+		SI_GBE@0x1000 0x2000
+		SI_ME@0x3000 0x2fed000
+		SI_PT@0x2ff0000 0x10000
+	}
+	RW_MRC_CACHE@0x3000000 0x18000
+	FMAP 0x1000
+	RW_VPD(PRESERVE) 0x4000
+	RO_VPD(PRESERVE) 0x4000
+	COREBOOT(CBFS)
+}
diff --git a/src/mainboard/bytedance/bd_egs/board_info.txt b/src/mainboard/bytedance/bd_egs/board_info.txt
new file mode 100644
index 0000000000..53d712378c
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: ByteDance
+Board name: bd_egs
+Category: eval
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
diff --git a/src/mainboard/bytedance/bd_egs/bootblock.c b/src/mainboard/bytedance/bd_egs/bootblock.c
new file mode 100644
index 0000000000..0ae8b1d800
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/bootblock.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/pcr.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <superio/aspeed/ast2400/ast2400.h>
+#include <superio/aspeed/common/aspeed.h>
+#include <soc/gpio.h>
+#include "gpio.h"
+
+#define ASPEED_SIO_PORT 0x2E
+#define PCR_DMI_LPCIOD  0x2770
+#define PCR_DMI_LPCIOE  0x2774
+
+void bootblock_mainboard_early_init(void)
+{
+	/*
+	 * Set up decoding windows on PCH over PCR. The CPU uses two of AST2600 SIO ports,
+	 * one is connected to debug header (SUART1) and another is used as SOL (SUART2).
+	 * For bd_egs, only SUART1 is used.
+	 */
+	uint16_t lpciod = (LPC_IOD_COMB_RANGE | LPC_IOD_COMA_RANGE);
+	uint16_t lpcioe = (LPC_IOE_SUPERIO_2E_2F | LPC_IOE_COMB_EN | LPC_IOE_COMA_EN);
+
+	/* Open IO windows: 0x3f8 for com1 and 02f8 for com2 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOD, lpciod);
+	/* LPC I/O enable: com1 and com2 */
+	pcr_or32(PID_DMI, PCR_DMI_LPCIOE, lpcioe);
+
+	/* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
+	pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
+
+	const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
+	aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
+
+	const struct pad_config *pads;
+	size_t pads_num;
+	pads = get_gpio_table(&pads_num);
+	gpio_configure_pads(pads, pads_num);
+}
diff --git a/src/mainboard/bytedance/bd_egs/devicetree.cb b/src/mainboard/bytedance/bd_egs/devicetree.cb
new file mode 100644
index 0000000000..eff12e13c2
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/devicetree.cb
@@ -0,0 +1,34 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip soc/intel/xeon_sp/spr
+	register "turbo_ratio_limit" = "0x181819191e242424"
+	register "turbo_ratio_limit_cores" = "0x3836322e2a1c1a18"
+
+	device domain 0 on
+		device pci 1f.0 on         # Intel device 1b81: PCH eSPI controller
+			chip superio/common
+				device pnp 2e.0 on
+					chip superio/aspeed/ast2400
+						register "use_espi" = "1"
+						device pnp 2e.2 on      # SUART1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.3 on      # SUART2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+					end
+				end
+			end
+			chip drivers/ipmi # BMC KCS
+				device pnp ca2.0 on end
+				register "bmc_i2c_address" = "0x20"
+				register "bmc_boot_timeout" = "60"
+			end
+			chip drivers/pc80/tpm # TPM
+				device pnp 0c31.0 on end
+			end
+		end
+	end
+end
diff --git a/src/mainboard/bytedance/bd_egs/dsdt.asl b/src/mainboard/bytedance/bd_egs/dsdt.asl
new file mode 100644
index 0000000000..544dc056a8
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <acpi/dsdt_top.asl>
+
+	#include "acpi/platform.asl"
+
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	#include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
+
+	Scope (\_SB.PC00)
+	{
+		#include <soc/intel/xeon_sp/spr/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/bytedance/bd_egs/gpio.c b/src/mainboard/bytedance/bd_egs/gpio.c
new file mode 100644
index 0000000000..d985b00b9b
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/gpio.c
@@ -0,0 +1,298 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include "gpio.h"
+
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF_OWNERSHIP(GPPC_A0, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_A1, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_A2, UP_20K, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_A3, UP_20K, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_A4, UP_20K, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_A5, UP_20K, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_A6, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_A7, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_A8, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_A9, DN_20K, DEEP, NF1, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A10, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A11, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPPC_A12, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A13, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A14, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPPC_A15, 1, DEEP),
+	PAD_CFG_GPIO_OWNERSHIP(GPPC_A16, NONE, DEEP, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A17, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A18, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_A19, NONE, DEEP, OFF, ACPI),
+
+	PAD_CFG_NF_OWNERSHIP(GPPC_B0, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B1, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B2, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B3, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B4, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B5, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B6, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B7, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B8, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B9, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B10, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B11, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B12, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B13, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B14, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B15, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B16, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B17, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B18, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B19, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B20, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_NMI(GPPC_B21, NONE, DEEP, LEVEL, INVERT),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B22, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B23, NONE, DEEP, OFF, ACPI),
+
+	PAD_CFG_NF_OWNERSHIP(GPPC_C0, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_C1, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPO(GPPC_C2, 1, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C3, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C4, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C5, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_C6, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_C7, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_C8, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C9, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C10, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPPC_C11, 1, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C12, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C13, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPPC_C14, 1, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C15, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C16, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPPC_C17, 1, PLTRST),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C18, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C19, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C20, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_C21, NONE, DEEP, OFF, ACPI),
+
+	PAD_CFG_NF_OWNERSHIP(GPP_D0, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D1, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPP_D3, 0, DEEP),
+	PAD_CFG_GPO(GPP_D4, 0, DEEP),
+	PAD_CFG_GPO(GPP_D5, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D6, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D7, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D8, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D9, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D11, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D12, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D13, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D14, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D15, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D16, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D17, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D20, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_D21, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, DEEP, OFF, ACPI),
+
+	PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPP_E4, 0, DEEP),			      // FIXME: GpioOutDefault
+	PAD_CFG_GPO(GPP_E5, 0, DEEP),			      // FIXME: GpioOutDefault
+	PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E8, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E9, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPP_E11, 0, DEEP),			      // FIXME: GpioOutDefault
+	PAD_CFG_GPI_TRIG_OWN(GPP_E12, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E14, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E18, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E19, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPP_E20, 0, DEEP),
+	PAD_CFG_GPO(GPP_E21, 0, DEEP),
+	PAD_CFG_GPO(GPP_E22, 0, DEEP),
+	PAD_CFG_GPO(GPP_E23, 0, DEEP),
+
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H0, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H1, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPPC_H2, 0, DEEP),
+	PAD_CFG_GPO(GPPC_H3, 0, DEEP),
+	PAD_CFG_GPO(GPPC_H4, 0, DEEP),
+	PAD_CFG_GPO(GPPC_H5, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H6, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H7, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPPC_H8, 0, DEEP),
+	PAD_CFG_GPO(GPPC_H9, 0, DEEP),
+	PAD_CFG_GPO(GPPC_H10, 0, DEEP),
+	PAD_CFG_GPO(GPPC_H11, 0, DEEP),
+	PAD_CFG_GPO(GPPC_H12, 0, DEEP),
+	PAD_CFG_GPO(GPPC_H13, 0, DEEP),
+	PAD_CFG_GPO(GPPC_H14, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H15, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H16, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H17, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H18, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_H19, NONE, DEEP, OFF, ACPI),
+
+	PAD_CFG_GPO(GPP_I0, 0, DEEP),
+	PAD_CFG_GPO(GPP_I1, 0, DEEP),
+	PAD_CFG_GPO(GPP_I2, 0, DEEP),
+	PAD_CFG_GPO(GPP_I3, 0, DEEP),
+	PAD_CFG_GPO(GPP_I4, 0, DEEP),
+	PAD_CFG_GPO(GPP_I5, 0, DEEP),
+	PAD_CFG_GPO(GPP_I6, 0, DEEP),
+	PAD_CFG_GPO(GPP_I7, 0, DEEP),
+	PAD_CFG_GPO(GPP_I8, 0, DEEP),
+	PAD_CFG_GPO(GPP_I9, 0, DEEP),
+	PAD_CFG_GPO(GPP_I10, 0, DEEP),
+	PAD_CFG_GPO(GPP_I11, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I12, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I13, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I14, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I15, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I16, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPP_I17, 0, DEEP),
+	PAD_CFG_GPO(GPP_I18, 0, DEEP),
+	PAD_CFG_GPO(GPP_I19, 0, DEEP),
+	PAD_CFG_GPO(GPP_I20, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I21, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I22, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I23, NONE, DEEP, OFF, ACPI),
+
+	PAD_CFG_NF_OWNERSHIP(GPP_J0, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_J1, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPO(GPP_J2, 0, DEEP),
+	PAD_CFG_NF_OWNERSHIP(GPP_J3, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_J4, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_J5, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_J6, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_J7, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_J8, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPO(GPP_J9, 0, DEEP),
+	PAD_CFG_GPO(GPP_J10, 0, DEEP),
+	PAD_CFG_GPO(GPP_J11, 0, DEEP),
+	PAD_CFG_NF_OWNERSHIP(GPP_J12, UP_20K, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_J13, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_J14, UP_20K, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_J15, UP_20K, DEEP, NF1, ACPI),
+	PAD_CFG_GPO(GPP_J16, 0, DEEP),
+	PAD_CFG_GPO(GPP_J17, 0, DEEP),
+
+	PAD_CFG_NF_OWNERSHIP(GPP_L0, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_L1, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_L2, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_L3, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_L4, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_L5, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_L6, NONE, DEEP, OFF, DRIVER),
+	PAD_CFG_GPI_TRIG_OWN(GPP_L7, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPP_L8, 0, DEEP),
+	PAD_CFG_GPO(GPP_L9, 0, DEEP),
+	PAD_CFG_GPO(GPP_L10, 0, DEEP),
+	PAD_CFG_GPO(GPP_L11, 0, DEEP),
+	PAD_CFG_GPO(GPP_L12, 0, DEEP),
+	PAD_CFG_GPO(GPP_L13, 0, DEEP),
+	PAD_CFG_GPO(GPP_L14, 0, DEEP),
+	PAD_CFG_GPO(GPP_L15, 0, DEEP),
+	PAD_CFG_GPO(GPP_L16, 0, DEEP),
+	PAD_CFG_GPO(GPP_L17, 0, DEEP),
+
+	PAD_CFG_GPI_TRIG_OWN(GPP_M0, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M1, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M2, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M3, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M4, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M5, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M6, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M7, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M8, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPP_M9, 0, DEEP),
+	PAD_CFG_GPO(GPP_M10, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M11, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M12, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPO(GPP_M13, 0, DEEP),
+	PAD_CFG_GPO(GPP_M14, 0, DEEP),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M15, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M16, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_M17, NONE, DEEP, OFF, ACPI),
+
+	PAD_CFG_GPO(GPP_N0, 0, DEEP),
+	PAD_CFG_GPO(GPP_N1, 0, DEEP),
+	PAD_CFG_GPO(GPP_N2, 0, DEEP),
+	PAD_CFG_GPO(GPP_N3, 0, DEEP),
+	PAD_CFG_GPO(GPP_N4, 0, DEEP),
+	PAD_CFG_GPO(GPP_N5, 0, DEEP),
+	PAD_CFG_GPO(GPP_N6, 0, DEEP),
+	PAD_CFG_GPO(GPP_N7, 0, DEEP),
+	PAD_CFG_GPO(GPP_N8, 0, DEEP),
+	PAD_CFG_GPO(GPP_N9, 0, DEEP),
+	PAD_CFG_GPO(GPP_N10, 0, DEEP),
+	PAD_CFG_GPO(GPP_N11, 0, DEEP),
+	PAD_CFG_GPO(GPP_N12, 0, DEEP),
+	PAD_CFG_GPO(GPP_N13, 0, DEEP),
+	PAD_CFG_GPO(GPP_N14, 0, DEEP),
+	PAD_CFG_GPO(GPP_N15, 0, DEEP),
+	PAD_CFG_GPO(GPP_N16, 0, DEEP),
+	PAD_CFG_GPO(GPP_N17, 0, DEEP),
+
+	PAD_CFG_GPI_TRIG_OWN(GPP_O1, NONE, PWROK, OFF, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O2, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O3, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O4, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O5, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O6, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_O7, NONE, PWROK, OFF, ACPI),
+	PAD_CFG_GPO(GPP_O8, 0, PWROK),
+	PAD_CFG_GPO(GPP_O9, 0, PWROK),
+	PAD_CFG_NF_OWNERSHIP(GPP_O10, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O11, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O12, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O13, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O14, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O15, NONE, PWROK, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPP_O16, NONE, PWROK, NF1, ACPI),
+
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S0, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_S1, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S2, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S3, NONE, RSMRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S4, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S5, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_S6, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_S7, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_S8, NONE, DEEP, NF1, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_S9, NONE, DEEP, NF1, DRIVER),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S10, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_S11, NONE, DEEP, OFF, ACPI),
+};
+
+static const struct pad_config override_fsp_gpio_table[] = {
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B10, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B11, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B12, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B13, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_NF_OWNERSHIP(GPPC_B14, NONE, DEEP, NF4, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPPC_B15, NONE, DEEP, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D22, NONE, DEEP, OFF, ACPI),
+};
+
+const struct pad_config *get_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *get_override_fsp_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_fsp_gpio_table);
+	return override_fsp_gpio_table;
+}
diff --git a/src/mainboard/bytedance/bd_egs/gpio.h b/src/mainboard/bytedance/bd_egs/gpio.h
new file mode 100644
index 0000000000..854a0f5b36
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/gpio.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _BD_EGS_GPIO_
+#define _BD_EGS_GPIO_
+
+#include <gpio.h>
+
+const struct pad_config *get_gpio_table(size_t *num);
+
+const struct pad_config *get_override_fsp_gpio_table(size_t *num);
+
+#endif /* _BD_EGS_GPIO_ */
diff --git a/src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h b/src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h
new file mode 100644
index 0000000000..b50e6f7bc5
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/include/sprsp_bd_iio.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SPRSP_BD_IIO_H_
+#define _SPRSP_BD_IIO_H_
+
+#include <defs_iio.h>
+
+/* For now only set 3 fields and hard-coded others, should be extended in the future */
+#define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp)	\
+	{						\
+		.SLOTEIP = 0,				\
+		.SLOTHPCAP = 0,				\
+		.SLOTHPSUP = 0,				\
+		.SLOTPIP = 0,				\
+		.SLOTAIP = 0,				\
+		.SLOTMRLSP = 0,				\
+		.SLOTPCP = 0,				\
+		.SLOTABP = 0,				\
+		.SLOTIMP = slotimp,			\
+		.SLOTSPLS = 0,				\
+		.SLOTSPLV = 0,				\
+		.SLOTPSP = slotpsp,			\
+		.VppEnabled = 0,			\
+		.VppPort = 0,				\
+		.VppAddress = 0,			\
+		.MuxAddress = 0,			\
+		.ChannelID = 0,				\
+		.PciePortEnable = 1,			\
+		.PEXPHIDE = pexphide,			\
+		.HidePEXPMenu = 0,			\
+		.PciePortOwnership = 0,			\
+		.RetimerConnectCount = 0,		\
+	}
+
+/*
+ * ByteDance IIO PCIe Port Table
+ */
+static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY bd_iio_pci_port_skt0[] = {
+	/* DMI port: array index 0 */
+	CFG_UPD_PCIE_PORT(0, 0, 0),
+	/* IOU0 (PE0): array index 1 ~ 8 */
+	CFG_UPD_PCIE_PORT(0, 1, 101), /* 15:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 103), /* 15:03.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 105), /* 15:05.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 107), /* 15:07.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU1 (PE1): array index 9 ~ 16 */
+	CFG_UPD_PCIE_PORT(0, 1, 109), /* 26:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 111), /* 26:03.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 113), /* 26:05.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 115), /* 26:07.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU2 (PE2): array index 17 ~ 24 */
+	CFG_UPD_PCIE_PORT(0, 1, 17), /* 37:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU3 (PE3): array index 25 ~ 32 */
+	CFG_UPD_PCIE_PORT(0, 1, 25), /* 48:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 129),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 131),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU4 (PE4): array index 33 ~ 40 */
+	CFG_UPD_PCIE_PORT(0, 1, 133), /* 59:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 135), /* 59:03.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 137), /* 59:05.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 139), /* 59:07.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* Bytedance doesn't use IOU5 ~ IOU6. */
+};
+
+static const UPD_IIO_PCIE_PORT_CONFIG_ENTRY bd_iio_pci_port_skt1[] = {
+	/* DMI port: array index 0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU0 (PE0): array index 1 ~ 8 */
+	CFG_UPD_PCIE_PORT(0, 1, 41), /* 97:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU1 (PE1): array index 9 ~ 16 */
+	CFG_UPD_PCIE_PORT(0, 1, 149), /* a7:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 151), /* a7:03.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 153), /* a7:05.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 155), /* a7:07.0 */
+	CFG_UPD_PCIE_PORT(0, 0, 0),
+	/* IOU2 (PE2): array index 17 ~ 24 */
+	CFG_UPD_PCIE_PORT(0, 1, 157), /* b7:01.0 */ //only use 1 x4.
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 1, 100),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 1, 100),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(1, 1, 100),
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU3 (PE3): array index 25 ~ 32 */
+	CFG_UPD_PCIE_PORT(0, 1, 165), /* c7:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 167), /* c7:03.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 169), /* c7:05.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 171), /* c7:07.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* IOU4 (PE4): array index 33 ~ 40 */
+	CFG_UPD_PCIE_PORT(0, 1, 173), /* d7:01.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 175), /* d7:03.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 177), /* d7:05.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	CFG_UPD_PCIE_PORT(0, 1, 179), /* d7:07.0 */
+	CFG_UPD_PCIE_PORT(1, 0, 0),
+	/* Bytedance doesn't use IOU5 ~ IOU6. */
+};
+#endif /* _SPRSP_BD_IIO_H_ */
diff --git a/src/mainboard/bytedance/bd_egs/ramstage.c b/src/mainboard/bytedance/bd_egs/ramstage.c
new file mode 100644
index 0000000000..dd19fc6a48
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/ramstage.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include <soc/gpio.h>
+
+#include "gpio.h"
+
+static void mainboard_chip_init(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t pads_num;
+
+	pads = get_gpio_table(&pads_num);
+	gpio_configure_pads(pads, pads_num);
+}
+
+void mainboard_override_fsp_gpio(void)
+{
+	const struct pad_config *pads;
+	size_t pads_num;
+
+	pads = get_override_fsp_gpio_table(&pads_num);
+	gpio_configure_pads(pads, pads_num);
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_chip_init,
+};
diff --git a/src/mainboard/bytedance/bd_egs/romstage.c b/src/mainboard/bytedance/bd_egs/romstage.c
new file mode 100644
index 0000000000..e010867b74
--- /dev/null
+++ b/src/mainboard/bytedance/bd_egs/romstage.c
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <soc/romstage.h>
+#include <defs_cxl.h>
+#include <defs_iio.h>
+#include <sprsp_bd_iio.h>
+
+static void mainboard_config_iio(FSPM_UPD *mupd)
+{
+	int port;
+
+	UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig =
+		(UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
+
+	/* Socket0: Array bd_iio_pci_port_skt0 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */
+	for (port = 0; port < ARRAY_SIZE(bd_iio_pci_port_skt0); port++) {
+		PciePortConfig[0].SLOTIMP[port] = bd_iio_pci_port_skt0[port].SLOTIMP;
+		PciePortConfig[0].SLOTPSP[port] = bd_iio_pci_port_skt0[port].SLOTPSP;
+		PciePortConfig[0].PciePortEnable[port] = bd_iio_pci_port_skt0[port].PciePortEnable;
+		PciePortConfig[0].PEXPHIDE[port] = bd_iio_pci_port_skt0[port].PEXPHIDE;
+		PciePortConfig[0].SLOTHPCAP[port] = bd_iio_pci_port_skt0[port].SLOTHPCAP;
+		PciePortConfig[0].VppPort[port] = bd_iio_pci_port_skt0[port].VppPort;
+		PciePortConfig[0].VppAddress[port] = bd_iio_pci_port_skt0[port].VppAddress;
+	}
+	/* Socket0: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */
+	for (port = ARRAY_SIZE(bd_iio_pci_port_skt0); port < MAX_IIO_PORTS_PER_SOCKET; port++) {
+		PciePortConfig[0].PEXPHIDE[port] = 1;
+		PciePortConfig[0].HidePEXPMenu[port] = 1;
+	}
+	PciePortConfig[0].ConfigIOU[0] = IIO_BIFURCATE_x4x4x4x4;
+	PciePortConfig[0].ConfigIOU[1] = IIO_BIFURCATE_x4x4x4x4;
+	PciePortConfig[0].ConfigIOU[2] = IIO_BIFURCATE_xxxxxx16;
+	PciePortConfig[0].ConfigIOU[3] = IIO_BIFURCATE_x4x4xxx8;
+	PciePortConfig[0].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4;
+
+	/* Socket1: Array bd_iio_pci_port_skt1 only configures DMI, IOU0 ~ IOU4, the rest will be left zero */
+	for (port = 0; port < ARRAY_SIZE(bd_iio_pci_port_skt1); port++) {
+		PciePortConfig[1].SLOTIMP[port] = bd_iio_pci_port_skt1[port].SLOTIMP;
+		PciePortConfig[1].SLOTPSP[port] = bd_iio_pci_port_skt1[port].SLOTPSP;
+		PciePortConfig[1].PciePortEnable[port] = bd_iio_pci_port_skt1[port].PciePortEnable;
+		PciePortConfig[1].PEXPHIDE[port] = bd_iio_pci_port_skt1[port].PEXPHIDE;
+		PciePortConfig[1].SLOTHPCAP[port] = bd_iio_pci_port_skt1[port].SLOTHPCAP;
+		PciePortConfig[1].VppPort[port] = bd_iio_pci_port_skt1[port].VppPort;
+		PciePortConfig[1].VppAddress[port] = bd_iio_pci_port_skt1[port].VppAddress;
+	}
+	/* Socket1: IOU5 ~ IOU6 are not used, set PEXPHIDE and HidePEXPMenu to 1 */
+	for (port = ARRAY_SIZE(bd_iio_pci_port_skt1); port < MAX_IIO_PORTS_PER_SOCKET; port++) {
+		PciePortConfig[1].PEXPHIDE[port] = 1;
+		PciePortConfig[1].HidePEXPMenu[port] = 1;
+	}
+	PciePortConfig[1].ConfigIOU[0] = IIO_BIFURCATE_xxxxxx16;
+	PciePortConfig[1].ConfigIOU[1] = IIO_BIFURCATE_x4x4x4x4;
+	PciePortConfig[1].ConfigIOU[2] = IIO_BIFURCATE_x4x4x4x4;
+	PciePortConfig[1].ConfigIOU[3] = IIO_BIFURCATE_x4x4x4x4;
+	PciePortConfig[1].ConfigIOU[4] = IIO_BIFURCATE_x4x4x4x4;
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	/* Disable CXL header bypass */
+	mupd->FspmConfig.DfxCxlHeaderBypass = 0;
+
+	/* Set DFX CXL security level to fully trusted */
+	mupd->FspmConfig.DfxCxlSecLvl = CXL_SECURITY_FULLY_TRUSTED;
+
+	/* Set DelayAfterPCIeLinkTraining to 2000 ms */
+	mupd->FspmConfig.DelayAfterPCIeLinkTraining = 2000;
+
+	mainboard_config_iio(mupd);
+}