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authorAngel Pons <th3fanbus@gmail.com>2020-10-01 22:50:12 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-11-03 17:04:03 +0000
commit3dea2b63eeb8f97b31571f6f0eb37f38f9967b6b (patch)
tree6d9843c11049d2ce89c55bd8deb451d542caee3c /src/mainboard/bostentech
parent88991caf00d3b8862bc3c1aa4497baeb67e910e6 (diff)
soc/intel/common/block/systemagent/memmap.c: Align cached region
When asked to place cbmem_top(), FSP does not seem to care about alignment. It can return an address that is MTRR poison, which will exhaust all variable MTRRs when trying to set up caching for CBMEM. This will make memory-mapped flash and TSEG caching fail as well. Safeguard against this by aligning the region to cache to half of its size, and move it upwards to compensate. It is assumed that caching memory above the provided bootloader TOLUM address is inconsequential. TEST=Boot Purism Librem Mini WHL, observe no MTRR exhaustion error messages in console. The boot process also feels more fluid. Change-Id: Ic64fd6d3d9e8ab4c78d68b910a476f9c4eb2d353 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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