mb/bostentech: Add GBYT4 port

- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook
	firmware)
	- Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick
- VGA: Video works with VGA rom extracted from UEFI
	- SeaBIOS (runs the option rom) tested, works in text mode
	- GRUB2 (coreboot runs the option rom) tested, works in VESA mode,
		no video in text mode
- USB: Both USB2.0 ports work using the EHCI controller
	- Works in both SeaBIOS, GRUB2 and Linux
- Serial: driven by an IT8728F SuperIO
	- Works as a console in coreboot, SeaBIOS and GRUB2
	- Works with interrupts in Linux after a cold boot, after a warm
		reboot IRQs get lost
- SATA: 2 ports on board (one is mSATA)
	- SATA init works with both refcode.elf and native refcode
		(patch CB:43133)
	- Booting from SATA works with GRUB2, SATA works in Linux
	- Patch CB:44088 fixes SATA in SeaBIOS
- 4 PCIe Intel ethernet controllers
	- Only tested in Linux, all 4 work with the igb driver
- Power button, reset button and both indicator LEDs work
- Optional fan header is not tested as the appliance is passively
	cooled
- TXE (ME): optional, does not shut down after 30 minutes without the
	TXE blob
	- Works with TXE blob left as is, shows up on PCI
	- Works with the entire TXE section wiped, no device on PCI,
		intelmetool can't find anything

Used rambi as an example, but almost everything is modified as the two
	boards are very different.

Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 90 insertions, 0 deletions

diff --git a/src/mainboard/bostentech/gbyt4/devicetree.cb b/src/mainboard/bostentech/gbyt4/devicetree.cb
new file mode 100644
index 0000000000..15a5d861da
--- /dev/null
+++ b/src/mainboard/bostentech/gbyt4/devicetree.cb
@@ -0,0 +1,90 @@
+chip soc/intel/baytrail
+
+	register "usb2_comp_bg" = "0x4700"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x3"
+	register "sata_ahci" = "0x1"
+
+	# Do not route USB ports to XHCI
+	register "usb_route_to_xhci" = "0"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 10.0 off end # MMC
+		device pci 11.0 off end # SDIO
+		device pci 12.0 off end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 off end # LPE
+		device pci 17.0 off end # MMC45
+		device pci 18.0 off end # SIO_DMA1
+		device pci 18.1 off end # I2C1
+		device pci 18.2 off end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off end # I2C5
+		device pci 18.6 off end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 off end # HDA
+		device pci 1c.0 on  end # PCI-e #1 (LAN1)
+		device pci 1c.1 on  end # PCI-e #2 (LAN2)
+		device pci 1c.2 on  end # PCI-e #3 (LAN3)
+		device pci 1c.3 on  end # PCI-e #4 (LAN4)
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 off end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+
+		device pci 1f.0 on      # LPC
+			chip superio/ite/it8728f
+				device pnp 2e.0 off end	# Floppy
+				device pnp 2e.1 on	# COM1
+					io  0x60 = 0x03f8
+					irq 0x70 = 4
+				end
+				device pnp 2e.2 off end	# COM2
+				device pnp 2e.3 off end	# Parallel port
+				device pnp 2e.4 on	# Environment Controller
+					io  0x60 = 0x0a30
+					irq 0x70 = 9
+					io  0x62 = 0x0a20
+				end
+				device pnp 2e.5 off end	# Keyboard
+				device pnp 2e.6 off end	# Mouse
+				device pnp 2e.7 off end	# GPIO
+				device pnp 2e.a off end	# CIR
+			end
+		end
+
+		device pci 1f.3 on  end # SMBus
+	end
+end