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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-05 14:23:14 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-24 10:36:42 +0000 |
commit | a7aa57a6ed22460f7d9df0019d157e1803a7cb8e (patch) | |
tree | 06faa2c62c0007596309e5c210fc9634e0f7aea3 /src/mainboard/biostar/am1ml/romstage.c | |
parent | f27cb243c2f7d11a46d38da9b960c3d8a5b05676 (diff) |
biostar/am1ml: Switch away from AGESA_LEGACY
Change-Id: I11ce2a558fe12f8f163dbe3dc52952a273b813ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/biostar/am1ml/romstage.c')
-rw-r--r-- | src/mainboard/biostar/am1ml/romstage.c | 112 |
1 files changed, 23 insertions, 89 deletions
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index f705b241aa..20708ccd47 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -14,27 +14,13 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <string.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> -#include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> -#include <cpu/amd/car.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesa_helper.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> +#include <northbridge/amd/agesa/state_machine.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include <cpu/amd/agesa/s3_resume.h> -#include "cbmem.h" #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> @@ -106,17 +92,13 @@ static void ite_gpio_conf(pnp_devfn_t dev) ite_exit_conf (dev); } - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { u32 val, t32; u8 byte; pci_devfn_t dev; u32 *addr32; - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. @@ -147,75 +129,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) t32 &= 0xffffbffb; *addr32 = t32; - if (!cpu_init_detectedx && boot_cpu()) { - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - post_code(0x30); - post_code(0x31); - - /* run ite */ - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - printk(BIOS_DEBUG, "Console inited!\n"); - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for(i = 0; i < 200000; i++) - val = inb(0xcd6); - - post_code(0x37); - agesawrapper_amdinitreset(); - post_code(0x38); - printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); - - post_code(0x39); - - agesawrapper_amdinitearly(); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - agesawrapper_amdinitpost(); - post_code(0x41); - agesawrapper_amdinitenv(); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - - amd_initcpuio(); - agesawrapper_amds3laterestore(); - - post_code(0x61); - prepare_for_resume(); - } + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); - post_code(0x50); /* This functions configure SIO as it been done under vendor bios */ printk(BIOS_DEBUG, "ITE CONFIG ENVC\n"); ite_evc_conf(ENVC_DEV); @@ -223,7 +147,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ite_gpio_conf(GPIO_DEV); printk(BIOS_DEBUG, "ITE CONFIG DONE\n"); - copy_and_run(); - post_code(0x54); /* Should never see this post code. */ + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ + int i; + for(i = 0; i < 200000; i++) + val = inb(0xcd6); + + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); + + post_code(0x50); } |