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| author | Furquan Shaikh <furquan@chromium.org> | 2016-10-24 15:23:40 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-10-26 01:50:36 +0200 |
| commit | aedbfc8f0917b332e648fe6c4333567bd8e58b0d (patch) | |
| tree | d56d052f2ecc6f6109a22060019e56c213a15249 /src/mainboard/bifferos/bifferboard/Kconfig | |
| parent | 5817a1555754709da92cae7f254d540e2b488cec (diff) | |
soc/intel/common: Enable support to write protect SPI flash range
Write-protect SPI flash range provided by caller by using a free Flash
Protected Range (FPR) register. This expects SoC to define a callback
for providing information about the first FPR register address and
maximum number of FPRs supported.
BUG=chrome-os-partner:58896
Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17115
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/bifferos/bifferboard/Kconfig')
0 files changed, 0 insertions, 0 deletions