diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2019-12-01 17:42:04 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-12 19:28:33 +0000 |
| commit | af258cc1791b5c46fcb13d41128cc99043a435be (patch) | |
| tree | 3c143244682d60fed4172086832ae9e4ad66fd76 /src/mainboard/bap | |
| parent | cbbfb702f693c1bbaf83a9d3d8a3c0caabda1814 (diff) | |
mb/*/*: use ACPIMMIO common block wherever possible
TEST=boot PC Engines apu2 and launch Debian Linux
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/bap')
| -rw-r--r-- | src/mainboard/bap/ode_e20XX/romstage.c | 4 | ||||
| -rw-r--r-- | src/mainboard/bap/ode_e21XX/romstage.c | 7 |
2 files changed, 5 insertions, 6 deletions
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index 505de38d9e..c1b96f1273 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -16,6 +16,7 @@ */ #include <arch/io.h> +#include <amdblocks/acpimmio.h> #include <device/pci_ops.h> #include <southbridge/amd/agesa/hudson/hudson.h> @@ -29,8 +30,7 @@ void board_BeforeAgesa(struct sysinfo *cb) { /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ - outb(0xea, 0xcd6); - outb(0x1, 0xcd7); + pm_io_write(0xea, 1); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 9729ffb400..a60e571367 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -14,6 +14,7 @@ */ #include <stdint.h> +#include <amdblocks/acpimmio.h> #include <device/pci_def.h> #include <arch/io.h> #include <arch/cpu.h> @@ -38,8 +39,7 @@ static void romstage_main_template(void) * the SoC BKDGs. Without this setting, there is no serial * output. */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); + pm_io_write8(0xd2, 0); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); @@ -52,6 +52,5 @@ static void romstage_main_template(void) void agesa_postcar(struct sysinfo *cb) { /* After AMD_INIT_ENV -> move to ramstage ? */ - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); + pm_io_write8(0xea, 1); } |