mainboard/bap: Add support for BAP ODE E20XX

Adding new board based on AMD Kabini.
Most of the code is copied from gizmosphere/gizmo2
Board is developed by BAP - Bruhnspace Advanced Projects:
http://www.unibap.com/ (Site is under construction)
Special on this board is:
-Soldered down memory
-SuperIO Fintek F81866D
Known bugs:
-S3 doesnt work
-Serial ports only works for the first boot. Needs power cut.
Tested with:
-SeaBios as Payload
-Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1
-Windows 8 64Bit

Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10288
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 6 insertions, 8 deletions

diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 4cfca8e320..2c2c4f1e17 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -2,6 +2,8 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+ * (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -35,21 +37,16 @@
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 #include <cpu/amd/agesa/s3_resume.h>
+#include <superio/fintek/common/fintek.h>
+#include <superio/fintek/f81866d/f81866d.h>
 #include "cbmem.h"
 
+#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	/* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
-	 *  LpcClk[1:0]".  To be consistent with Parmer, setting to 4mA
-	 *  even though the register is not documented in the Kabini BKDG.
-	 *  Otherwise the serial output is bad code.
-	 */
-	outb(0xD2, 0xcd6);
-	outb(0x00, 0xcd7);
-
 	amd_initmmio();
 
 	/* Set LPC decode enables. */
@@ -62,6 +59,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		post_code(0x30);
 
 		post_code(0x31);
+		fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
 		console_init();
 	}