diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-03-04 07:33:45 +0200 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-08-24 10:31:06 +0000 |
commit | 65200be7fe6aba9f9a9b8f9e00fcab12fdca5ccd (patch) | |
tree | cc8bd8fbc0ca4be1ba444d88ac2dd9d8ec7b44ff /src/mainboard/bap/ode_e20XX/OemCustomize.c | |
parent | 6dcd4bcf772745c5d686117e6558e9dc91875295 (diff) |
bap/ode_e20XX: Switch away from AGESA_LEGACY_WRAPPER
Change-Id: Ia747b3bc149a672a6de2ecf0308141172321a493
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/bap/ode_e20XX/OemCustomize.c')
-rw-r--r-- | src/mainboard/bap/ode_e20XX/OemCustomize.c | 35 |
1 files changed, 20 insertions, 15 deletions
diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c index 752293a031..00d51b6b27 100644 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c @@ -20,7 +20,7 @@ #include <PlatformMemoryConfiguration.h> #include "Filecode.h" -#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -89,6 +89,13 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = DdiList }; +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = FALSE; +} + /*---------------------------------------------------------------------------------------*/ /** * OemCustomizeInitEarly @@ -105,7 +112,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -127,14 +134,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -148,7 +147,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_WL 0x0E WRITE_LEVELING_SEED( @@ -174,7 +173,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} |