amd/geode_lx: Remove most boards

There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.

Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

10 files changed, 0 insertions, 371 deletions

diff --git a/src/mainboard/bachmann/Kconfig b/src/mainboard/bachmann/Kconfig
deleted file mode 100644
index 27831d1adc..0000000000
--- a/src/mainboard/bachmann/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_BACHMANN
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/bachmann/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/bachmann/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	string
-	default "Bachmann electronic"
-
-endif # VENDOR_BACHMANN
diff --git a/src/mainboard/bachmann/ot200/Kconfig b/src/mainboard/bachmann/ot200/Kconfig
deleted file mode 100644
index 3ca0384d2d..0000000000
--- a/src/mainboard/bachmann/ot200/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
-if BOARD_BACHMANN_OT200
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_GEODE_LX
-	select NORTHBRIDGE_AMD_LX
-	select SOUTHBRIDGE_AMD_CS5536
-	select HAVE_PIRQ_TABLE
-	select PIRQ_ROUTE
-	select UDELAY_TSC
-	select BOARD_ROMSIZE_KB_2048
-	select POWER_BUTTON_DEFAULT_DISABLE
-	select PLL_MANUAL_CONFIG
-	select CORE_GLIU_500_266
-	select HAVE_OPTION_TABLE
-	select HAVE_CMOS_DEFAULT
-
-config MAINBOARD_DIR
-	string
-	default bachmann/ot200
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "OT200"
-
-config IRQ_SLOT_COUNT
-	int
-	default 6
-
-config PLLMSRlo
-	hex
-	default 0x07de001e
-
-endif # BOARD_BACHMANN_OT200
diff --git a/src/mainboard/bachmann/ot200/Kconfig.name b/src/mainboard/bachmann/ot200/Kconfig.name
deleted file mode 100644
index 4b63f968b2..0000000000
--- a/src/mainboard/bachmann/ot200/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_BACHMANN_OT200
-	bool "OT200"
diff --git a/src/mainboard/bachmann/ot200/board_info.txt b/src/mainboard/bachmann/ot200/board_info.txt
deleted file mode 100644
index 0ba2657f1a..0000000000
--- a/src/mainboard/bachmann/ot200/board_info.txt
+++ /dev/null
@@ -1 +0,0 @@
-Category: settop
diff --git a/src/mainboard/bachmann/ot200/cmos.default b/src/mainboard/bachmann/ot200/cmos.default
deleted file mode 100644
index 3e6d135052..0000000000
--- a/src/mainboard/bachmann/ot200/cmos.default
+++ /dev/null
@@ -1,2 +0,0 @@
-boot_option=Fallback
-debug_level=Spew
diff --git a/src/mainboard/bachmann/ot200/cmos.layout b/src/mainboard/bachmann/ot200/cmos.layout
deleted file mode 100644
index 88b1c64c21..0000000000
--- a/src/mainboard/bachmann/ot200/cmos.layout
+++ /dev/null
@@ -1,50 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Bachmann electronic GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-entries
-
-# -----------------------------------------------------------------
-# RTC reserved
-0          384       r       0        reserved_memory
-
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392          3       r       0        unused
-395          4       e       2        debug_level
-
-# -----------------------------------------------------------------
-# coreboot config options: check sums
-1008         16      h       0        check_sum
-
-enumerations
-
-#ID value   text
-2     0     Emergency
-2     1     Alert
-2     2     Critical
-2     3     Error
-2     4     Warning
-2     5     Notice
-2     6     Info
-2     7     Debug
-2     8     Spew
-4     0     Fallback
-4     1     Normal
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/bachmann/ot200/devicetree.cb b/src/mainboard/bachmann/ot200/devicetree.cb
deleted file mode 100644
index 1e61b3d357..0000000000
--- a/src/mainboard/bachmann/ot200/devicetree.cb
+++ /dev/null
@@ -1,40 +0,0 @@
-chip northbridge/amd/lx
-	device domain 0 on
-		device pci 1.0 on end	# Northbridge
-		device pci 1.1 on end	# Graphics
-		device pci 1.2 on end   # AES
-		chip southbridge/amd/cs5536
-			register "lpc_serirq_enable" = "0x00000000"
-			register "lpc_serirq_polarity" = "0x00000000"
-			register "lpc_serirq_mode" = "0"
-			register "enable_gpio_int_route" = "0x0C0D0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "1"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "1"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci 4.0 on end	# Ethernet 0
-			device pci f.0 on	# ISA Bridge
-				chip drivers/generic/generic        # eeprom
-					device i2c 52 on end
-				end
-			end
-			device pci f.2 on end	# IDE Controller
-			device pci f.3 on end	# Audio
-			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-			device pci f.7 on end	# UOC
-		end
-	end
-	# APIC cluster is late CPU init.
-	device cpu_cluster 0 on
-		chip cpu/amd/geode_lx
-			device lapic 0 on end
-		end
-	end
-end
diff --git a/src/mainboard/bachmann/ot200/irq_tables.c b/src/mainboard/bachmann/ot200/irq_tables.c
deleted file mode 100644
index 541861300a..0000000000
--- a/src/mainboard/bachmann/ot200/irq_tables.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Bachmann electronic GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-/* Platform IRQs */
-#define PIRQA 5
-#define PIRQB 9
-#define PIRQC 10
-#define PIRQD 7
-
-/* Map */
-#define M_PIRQA (1 << PIRQA)	/* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB)	/* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC)	/* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD)	/* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA  1		/* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB  2		/* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC  3		/* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD  4		/* Means Slot INTx# Connects To Chipset INTD# */
-
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,				/* u32 signature */
-	PIRQ_VERSION,				/* u16 version */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* Max. number of devices on the bus */
-	0x00,					/* Interrupt router bus */
-	0x0f << 3,				/* Interrupt router dev */
-	0,					/* IRQs devoted exclusively to PCI usage */
-	0x100b,					/* Vendor */
-	0x2b,					/* Device */
-	0,					/* Miniport */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	/* u8 rfu[11] */
-	0x20,					/* Checksum (has to be set to some value that
-						 * would give 0 after the sum of all bytes
-						 * for this structure (including checksum).
-						 */
-	{
-		/* bus,        dev | fn,   {link, bitmap},     {link, bitmap},     {link, bitmap},     {link, bitmap},      slot, rfu */
-		{0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000},     {0x00, 0x0000},     {0x00, 0x0000}},     0x0, 0x0},	/* CPU */
-		{0x00, (0x0f << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
-		{0x00, (0x04 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x0000},     {0x00, 0x0000},     {0x00, 0x0000}},     0x0, 0x0},	/* ethernet */
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c
deleted file mode 100644
index 80fc2c6a4a..0000000000
--- a/src/mainboard/bachmann/ot200/mainboard.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Bachmann electronic GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <device/smbus.h>
-#include <smbios.h>
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <arch/io.h>
-
-/* overwrite a weak function to fill SMBIOS table with a custom value */
-static u8 hw_rev = 0;
-static char mb_rev_str[2] = { '0' };
-
-const char *smbios_mainboard_version(void)
-{
-	/* UDMA is not working on all supported devices */
-	if (hw_rev < 113) {
-		mb_rev_str[0] = '1';
-	} else {
-		mb_rev_str[0] = '2';
-	}
-
-	return mb_rev_str;
-}
-
-static void init(struct device *dev)
-{
-	unsigned int i;
-	u32 chksum = 0;
-	char block[20];
-	msr_t reset;
-	device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52);
-
-	if (eeprom_dev == 0) {
-		printk(BIOS_WARNING, "eeprom not found\n");
-		return;
-	}
-
-	/* turn off all leds except led_ini */
-	outb(0x02, 0x5a); /* bit0 - led_run */
-			  /* bit1 - led_ini */
-			  /* bit2 - led_err */
-			  /* bit3-bit7 - write has no effect */
-	outb(0x00, 0x49); /* bit0-bit6 - led_7-led_1 */
-			  /* bit7 - write has no effect */
-
-	/* read the whole block and check if checksum is okay */
-	for (i = 0; i < 20; i++) {
-		block[i] = smbus_read_byte(eeprom_dev, i);
-		chksum += block[i];
-	}
-
-	if (chksum != 0) {
-		printk(BIOS_WARNING, "wrong checksum: 0x%0x\n", chksum);
-	}
-
-	hw_rev = block[5];
-
-	printk(BIOS_DEBUG, "hw revision: %u\n", hw_rev);
-
-	/* Reset MFGPT7 (standby power domain) - this is done via
-	 * an undocumented register */
-	reset = rdmsr(0x5140002b);
-	reset.lo |= 1 << 7;
-	wrmsr(0x5140002b, reset);
-}
-
-static void mainboard_enable(struct device *dev)
-{
-	dev->ops->init = init;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c
deleted file mode 100644
index 410c978eba..0000000000
--- a/src/mainboard/bachmann/ot200/romstage.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Bachmann electronic GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <stdlib.h>
-#include <stdint.h>
-#include <spd.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/car.h>
-#include <cpu/amd/lxdef.h>
-#include <southbridge/amd/cs5536/cs5536.h>
-#include <northbridge/amd/lx/raminit.h>
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-void asmlinkage mainboard_romstage_entry(unsigned long bist)
-{
-	static const struct mem_controller memctrl[] = {
-		{.channel0 = {DIMM0}}
-	};
-
-	SystemPreInit();
-	msr_init();
-
-	cs5536_early_setup();
-
-	/* Note: must do this AFTER the early_setup! It is counting on some
-	 * early MSR setup for CS5536.
-	 */
-	/* cs5536_disable_internal_uart: disable them for now, set them
-	 * up later...
-	 */
-	/* If debug. real setup done in chipset init via devicetree.cb. */
-	cs5536_setup_onchipuart(1);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	pll_reset();
-
-	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
-	sdram_initialize(1, memctrl);
-
-	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
-	return;
-}