Add support for the AXUS TC320 thin client.

This board uses nearly the same devices as the BCOM Winnet100, so most of
the new code here is from the BCOM Winnet100. They differ in the IRQ routing
table only.

BTW: The AXUS board uses standard DIMM memory and can be run at 100MHz SDRAM
clock speed (it runs reliably here since month).

Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 135 insertions, 0 deletions

diff --git a/src/mainboard/axus/tc320/Config.lb b/src/mainboard/axus/tc320/Config.lb
new file mode 100644
index 0000000000..d7b0a7880a
--- /dev/null
+++ b/src/mainboard/axus/tc320/Config.lb
@@ -0,0 +1,135 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
+else
+	default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
+	default ROM_SECTION_OFFSET = 0
+end
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE
+				   + ROM_SECTION_OFFSET + 1)
+default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+default XIP_ROM_SIZE = 64 * 1024
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+arch i386 end
+driver mainboard.o
+if HAVE_PIRQ_TABLE object irq_tables.o end
+makerule ./failover.E
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+	action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./failover.inc
+	depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ./romcc"
+	action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
+end
+makerule ./auto.E
+	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	depends	"$(MAINBOARD)/auto.c ./romcc"
+	action	"./romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+	# depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+	depends "$(MAINBOARD)/auto.c ./romcc"
+	action	"./romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
+else
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
+end
+mainboardinit arch/i386/lib/cpu_reset.inc
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds
+	mainboardinit ./failover.inc
+end
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/amd/model_gx1/cpu_setup.inc
+mainboardinit cpu/amd/model_gx1/gx_setup.inc
+mainboardinit ./auto.inc
+
+dir /pc80
+config chip.h
+
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc97317	# Super I/O
+          device pnp 2e.0 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.1 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.2 on		# RTC, advanced power control (APC)
+            io 0x60 = 0x70
+            irq 0x70 = 8
+          end
+          device pnp 2e.3 off		# Floppy (N/A on this board)
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.4 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.5 off		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.6 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.7 on		# GPIO
+            io 0x60 = 0xe0
+          end
+          device pnp 2e.8 on		# Power management
+            io 0x60 = 0xe800
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 off end		# IDE
+      device pci 12.3 on end		# Audio
+      device pci 12.4 on end		# VGA (onboard)
+      device pci 13.0 on end		# USB
+      # register "ide0_enable" = "1"
+      # register "ide1_enable" = "1"
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end