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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-06 15:27:27 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-19 16:16:44 +0000 |
| commit | acfc149f7b16ef40816e3d5d4c2f8452fe9dd091 (patch) | |
| tree | aa0fe466beffbe71b9912d677fd3fa2864f88ec7 /src/mainboard/avalue | |
| parent | 6228b9efb7f2fda1d248fb2fa320bf8cf2da55f8 (diff) | |
soc/intel/cannonlake: Add microcode support
Microcode needs to be loaded prior to FSP initialization.
Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20484
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/avalue')
0 files changed, 0 insertions, 0 deletions