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authorAngel Pons <th3fanbus@gmail.com>2022-05-02 16:52:57 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-05-04 13:11:00 +0000
commitf0ed846cfce843965f191e56ba01b35d8c9195b0 (patch)
treead0130fc28ff0db07e7fa2a25a8b15c20116bc10 /src/mainboard/asus
parent33377f1b2c79cf1e6fca8c2170c4a0a5da04ec0a (diff)
arch/x86/acpi: Consolidate POST code handling
Move ASL POST code declarations into a common file to avoid redundancy. Also, provide a dummy implementation when `POST_IO` is not enabled, as the value of `CONFIG_POST_IO_PORT` can't be used. Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r--src/mainboard/asus/p2b/dsdt.asl8
1 files changed, 1 insertions, 7 deletions
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index 25515d22e9..5d53c1dfa6 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -22,13 +22,7 @@ DefinitionBlock (
#include <acpi/dsdt_top.asl>
/* \_SB scope defining the main processor is generated in SSDT. */
- /* Port 80 POST */
-
- OperationRegion (POST, SystemIO, 0x80, 1)
- Field (POST, ByteAcc, Lock, Preserve)
- {
- DBG0, 8
- }
+ #include <arch/x86/acpi/post.asl>
/*
* Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142