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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-03-20 13:56:46 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 10:43:37 +0000 |
| commit | 9550e97304ecc1c1b6271d50ea089c82b9a82946 (patch) | |
| tree | 47d39123eae170fe1a014b8bdde8d96a17f7943c /src/mainboard/asus | |
| parent | a956063e5f9c19179e4bacd145e26e159f1982b2 (diff) | |
acpi: correct the processor devices scope
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here.
Additionally add processor scope patching for P-State SSDT created by
AGESA, becasue AGESA creates the tables with processors in \_PR scope.
TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are
no errors, decompile ACPI tables with acpica to check whether the
processor scope is correct and if IASL does not complain on wrong
checksum, run FWTS
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/am1i-a/dsdt.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/asus/f2a85-m/acpi/cpstate.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/asus/f2a85-m/dsdt.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/asus/p2b-ls/dsdt.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/asus/p2b/dsdt.asl | 2 |
5 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl index fcae00b660..2d55f7cf58 100644 --- a/src/mainboard/asus/am1i-a/dsdt.asl +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -31,7 +31,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl index c88aa64bcf..4a49f6baf2 100644 --- a/src/mainboard/asus/f2a85-m/acpi/cpstate.asl +++ b/src/mainboard/asus/f2a85-m/acpi/cpstate.asl @@ -21,7 +21,7 @@ #include <arch/acpi.h> DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001) { - Scope (\_PR) { + Scope (\_SB) { Device (CPU0) { Name (_HID, "ACPI0007") Name (_UID, 0) diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl index ad9ce1bc21..f34ccc8244 100644 --- a/src/mainboard/asus/f2a85-m/dsdt.asl +++ b/src/mainboard/asus/f2a85-m/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include <cpu/amd/agesa/family15tn/acpi/cpu.asl> /* Describe the supported Sleep States for this Southbridge */ diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 938caa5a7c..c79b78649f 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -23,7 +23,7 @@ #include <arch/acpi.h> DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) { - /* \_PR scope defining the main processor is generated in SSDT. */ + /* \_SB scope defining the main processor is generated in SSDT. */ OperationRegion(X80, SystemIO, 0x80, 1) Field(X80, ByteAcc, NoLock, Preserve) diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index c67e50fd79..b52b456983 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -23,7 +23,7 @@ #include <arch/acpi.h> DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) { - /* \_PR scope defining the main processor is generated in SSDT. */ + /* \_SB scope defining the main processor is generated in SSDT. */ OperationRegion(X80, SystemIO, 0x80, 1) Field(X80, ByteAcc, NoLock, Preserve) |