mb/asus/p8z77-v_lx2: Extract overridetree

Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-V LX2
remains identical when not adding the .config file in it.

Change-Id: Ia84b07f5fec3c2969134b0d0bc39248d50ac04ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

3 files changed, 68 insertions, 36 deletions

diff --git a/src/mainboard/asus/p8z77-series/Kconfig b/src/mainboard/asus/p8z77-series/Kconfig
index d09b3cb7b5..d963b09651 100644
--- a/src/mainboard/asus/p8z77-series/Kconfig
+++ b/src/mainboard/asus/p8z77-series/Kconfig
@@ -29,10 +29,22 @@ config MAINBOARD_PART_NUMBER
 	default "P8Z77-M PRO" if BOARD_ASUS_P8Z77_M_PRO
 	default "P8Z77-V LX2" if BOARD_ASUS_P8Z77_V_LX2
 
+# TODO: remove once all boards use overridetrees
+if BOARD_ASUS_P8Z77_M_PRO
+
 config DEVICETREE
 	string
 	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
 
+endif
+if !BOARD_ASUS_P8Z77_M_PRO
+
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+endif
+
 config CMOS_DEFAULT_FILE
 	default "src/mainboard/\$(MAINBOARDDIR)/variants/\$(CONFIG_VARIANT_DIR)/cmos.default"
 
diff --git a/src/mainboard/asus/p8z77-series/devicetree.cb b/src/mainboard/asus/p8z77-series/devicetree.cb
new file mode 100644
index 0000000000..1b9d14d4f4
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/devicetree.cb
@@ -0,0 +1,56 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	device cpu_cluster 0 on
+		chip cpu/intel/model_206ax
+			register "acpi_c1" = "1"
+			register "acpi_c2" = "3"
+			register "acpi_c3" = "5"
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
+	end
+	device domain 0 on
+		device pci 00.0 on  end		# Host bridge
+		device pci 01.0 on  end		# PCIEX16_1
+		device pci 02.0 on  end		# iGPU
+
+		chip southbridge/intel/bd82x6x
+			register "c2_latency" = "0x0065"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x3f"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+			register "superspeed_capable_ports" = "0x0000000f"
+			register "xhci_overcurrent_mapping" = "0x00000c03"
+			register "xhci_switchable_ports"    = "0x0000000f"
+
+			device pci 14.0 on  end		# xHCI
+			device pci 16.0 on  end		# MEI #1
+			device pci 16.1 off end		# MEI #2
+			device pci 16.2 off end		# ME IDE-R
+			device pci 16.3 off end		# ME KT
+			device pci 19.0 off end		# Intel GbE
+			device pci 1a.0 on  end		# EHCI #2
+			device pci 1b.0 on  end		# HD Audio
+
+			device pci 1c.0 off end		# RP #1
+			device pci 1c.1 off end		# RP #2
+			device pci 1c.2 off end		# RP #3
+			device pci 1c.3 off end		# RP #4
+			device pci 1c.4 off end		# RP #5
+			device pci 1c.5 off end		# RP #6
+			device pci 1c.6 off end		# RP #7
+			device pci 1c.7 off end		# RP #8
+
+			device pci 1d.0 on  end		# EHCI #1
+			device pci 1e.0 off end		# PCI bridge
+			device pci 1f.0 on		# LPC bridge
+			end
+			device pci 1f.2 on  end		# SATA (AHCI)
+			device pci 1f.3 on  end		# SMBus
+			device pci 1f.5 off end		# SATA (Legacy)
+			device pci 1f.6 off end		# Thermal
+		end
+	end
+end
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/overridetree.cb
index 40f8e6db2b..6be23faf87 100644
--- a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/devicetree.cb
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/overridetree.cb
@@ -1,40 +1,10 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 chip northbridge/intel/sandybridge
-	device cpu_cluster 0 on
-		chip cpu/intel/model_206ax
-			register "acpi_c1" = "1"
-			register "acpi_c2" = "3"
-			register "acpi_c3" = "5"
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
-	end
 	device domain 0 on
 		subsystemid 0x1043 0x84ca inherit
-		device pci 00.0 on  end		# Host bridge
-		device pci 01.0 on  end		# PCIEX16_1
-		device pci 02.0 on  end		# iGPU
-
 		chip southbridge/intel/bd82x6x
-			register "c2_latency" = "0x0065"
 			register "gen1_dec" = "0x000c0291"
-			register "sata_interface_speed_support" = "0x3"
-			register "sata_port_map" = "0x3f"
-			register "spi_lvscc" = "0x2005"
-			register "spi_uvscc" = "0x2005"
-			register "superspeed_capable_ports" = "0x0000000f"
-			register "xhci_overcurrent_mapping" = "0x00000c03"
-			register "xhci_switchable_ports"    = "0x0000000f"
-
-			device pci 14.0 on  end		# xHCI
-			device pci 16.0 on  end		# MEI #1
-			device pci 16.1 off end		# MEI #2
-			device pci 16.2 off end		# ME IDE-R
-			device pci 16.3 off end		# ME KT
-			device pci 19.0 off end		# Intel GbE
-			device pci 1a.0 on  end		# EHCI #2
-			device pci 1b.0 on  end		# HD Audio
 
 			device pci 1c.0 on  end		# RP #1: PCIEX16_2 (electrical x4)
 			device pci 1c.1 off end		# RP #2:
@@ -45,8 +15,6 @@ chip northbridge/intel/sandybridge
 			device pci 1c.6 on  end		# RP #7: PCIEX1_1
 			device pci 1c.7 on  end		# RP #8: PCIEX1_2
 
-			device pci 1d.0 on  end		# EHCI #1
-			device pci 1e.0 off end		# PCI bridge
 			device pci 1f.0 on		# LPC bridge
 				chip superio/nuvoton/nct6779d
 					device pnp 2e.1   off end	# Parallel
@@ -88,10 +56,6 @@ chip northbridge/intel/sandybridge
 					device pnp 2e.16  off end	# Deep Sleep
 				end
 			end
-			device pci 1f.2 on  end		# SATA (AHCI)
-			device pci 1f.3 on  end		# SMBus
-			device pci 1f.5 off end		# SATA (Legacy)
-			device pci 1f.6 off end		# Thermal
 		end
 	end
 end