diff options
author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-07 21:43:48 +0000 |
---|---|---|
committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-02-07 21:43:48 +0000 |
commit | abf2ad716daff751d75907d47bcae4a7044fd7b4 (patch) | |
tree | f82427b43d76a4791253373affed1af8669e2e7b /src/mainboard/asus | |
parent | 389240f288b2708617a35ebe8d7f89b3bff316c5 (diff) |
newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r-- | src/mainboard/asus/a8n_e/Config.lb | 241 | ||||
-rw-r--r-- | src/mainboard/asus/a8n_e/Options.lb | 168 | ||||
-rw-r--r-- | src/mainboard/asus/a8v-e_se/Config.lb | 190 | ||||
-rw-r--r-- | src/mainboard/asus/a8v-e_se/Options.lb | 165 | ||||
-rw-r--r-- | src/mainboard/asus/m2v-mx_se/Config.lb | 167 | ||||
-rw-r--r-- | src/mainboard/asus/m2v-mx_se/Options.lb | 174 | ||||
-rw-r--r-- | src/mainboard/asus/mew-am/Config.lb | 135 | ||||
-rw-r--r-- | src/mainboard/asus/mew-am/Options.lb | 97 | ||||
-rw-r--r-- | src/mainboard/asus/mew-vm/Config.lb | 147 | ||||
-rw-r--r-- | src/mainboard/asus/mew-vm/Options.lb | 154 | ||||
-rw-r--r-- | src/mainboard/asus/p2b-d/Config.lb | 134 | ||||
-rw-r--r-- | src/mainboard/asus/p2b-d/Options.lb | 103 | ||||
-rw-r--r-- | src/mainboard/asus/p2b-ds/Config.lb | 135 | ||||
-rw-r--r-- | src/mainboard/asus/p2b-ds/Options.lb | 104 | ||||
-rw-r--r-- | src/mainboard/asus/p2b-f/Config.lb | 132 | ||||
-rw-r--r-- | src/mainboard/asus/p2b-f/Options.lb | 97 | ||||
-rw-r--r-- | src/mainboard/asus/p2b/Config.lb | 132 | ||||
-rw-r--r-- | src/mainboard/asus/p2b/Options.lb | 98 | ||||
-rw-r--r-- | src/mainboard/asus/p3b-f/Config.lb | 133 | ||||
-rw-r--r-- | src/mainboard/asus/p3b-f/Options.lb | 97 |
20 files changed, 0 insertions, 2803 deletions
diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb deleted file mode 100644 index 374629c5b3..0000000000 --- a/src/mainboard/asus/a8n_e/Config.lb +++ /dev/null @@ -1,241 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) -## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> -## (Thanks to LSRA University of Mannheim for their support) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/failovercalculation.lb - -arch i386 end -driver mainboard.o -# Needed by irq_tables and mptable and acpi_tables. -object get_bus_conf.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - if CONFIG_USE_INIT - makerule ./auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - end -end -mainboardinit cpu/x86/32bit/entry32.inc - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - ldscript /cpu/amd/car/cache_as_ram.lds - end -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds - else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds - end -end -# Include an ID string (for safe flashing). -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -# ROMSTRAP table for CK804. -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - mainboardinit southbridge/nvidia/ck804/romstrap.inc - ldscript /southbridge/nvidia/ck804/romstrap.lds - end -end - mainboardinit cpu/amd/car/cache_as_ram.inc -if CONFIG_HAVE_FAILOVER_BOOT - if CONFIG_USE_FAILOVER_IMAGE - ldscript /arch/i386/lib/failover_failover.lds - end -else - if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - end -end - if CONFIG_USE_INIT - initobject auto.o - else - mainboardinit ./auto.inc - end -config chip.h - -chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # Socket 939 CPU - device apic 0 on end # APIC - end - end - - device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x0000 - irq 0x70 = 0x00 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x71 = 2 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - irq 0x71 = 2 - end - device pnp 2e.7 on # GPIO config - io 0x60 = 0x0800 - # Set GPIO 1 & 2 - io 0x25 = 0x0000 - # Set GPIO 3 & 4 - io 0x27 = 0x2540 - # GPIO Polarity for Set 3 - io 0xb2 = 0x2100 - # GPIO Pin Internal Pull up for Set 3 - io 0xba = 0x0100 - # Simple I/O register config - io 0xc0 = 0x0000 - io 0xc2 = 0x2540 - io 0xc8 = 0x0000 - io 0xca = 0x0500 - end - device pnp 2e.8 on # Midi port - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.a off # IR (N/A on this board) - io 0x60 = 0x310 - irq 0x70 = 11 - end - end - end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic #dimm 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic #dimm 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic #dimm 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic #dimm 0-1-1 - # device i2c 53 on end - # end - # chip drivers/generic/generic #dimm 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic #dimm 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic #dimm 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic #dimm 1-1-1 - # device i2c 57 on end - # end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI), N/A - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 on end # PCI E 3 - device pci c.0 on end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # register "mac_eeprom_smbus" = "3" - # register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb deleted file mode 100644 index a03db4bb0b..0000000000 --- a/src/mainboard/asus/a8n_e/Options.lb +++ /dev/null @@ -1,168 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de> -## (Thanks to LSRA University of Mannheim for their support) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_USE_FAILOVER_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_FAILOVER_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_FAILOVER_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_CONSOLE_BTEXT -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_HW_MEM_HOLE_SIZEK -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_USE_INIT -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_AP_CODE_IN_CAR -uses CONFIG_MEM_TRAIN_SEQ -uses CONFIG_WAIT_BEFORE_CPUS_INIT -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID -uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_USE_PRINTK_IN_CAR -uses CONFIG_ID_SECTION_OFFSET - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_FAILOVER_SIZE = 4 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_FAILOVER_BOOT = 1 -default CONFIG_HAVE_HARD_RESET = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 13 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_HAVE_OPTION_TABLE = 1 -# Move the default coreboot CMOS range off of AMD RTC registers. -default CONFIG_LB_CKS_RANGE_START = 49 -default CONFIG_LB_CKS_RANGE_END = 122 -default CONFIG_LB_CKS_LOC = 123 -# SMP support (only worry about 2 micro processors). -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_MAX_PHYSICAL_CPUS = 1 -default CONFIG_LOGICAL_CPUS = 1 -# 1G memory hole. -default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000 -# HT Unit ID offset, default is 1, the typical one. -default CONFIG_HT_CHAIN_UNITID_BASE = 0 -# Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10 -# Make the SB HT chain on bus 0, default is not (0). -default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2 -# Only offset for SB chain?, default is yes(1). -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 -# default CONFIG_CONSOLE_BTEXT = 1 # BTEXT console -default CONFIG_CONSOLE_VGA = 1 # For VGA console -default CONFIG_PCI_ROM_RUN = 1 # For VGA console -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xc8000 -default CONFIG_DCACHE_RAM_SIZE = 32 * 1024 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024 -default CONFIG_USE_INIT = 0 -default CONFIG_AP_CODE_IN_CAR = 0 -default CONFIG_MEM_TRAIN_SEQ = 2 -default CONFIG_WAIT_BEFORE_CPUS_INIT = 0 -# default CONFIG_ENABLE_APIC_EXT_ID = 0 -# default CONFIG_APIC_ID_OFFSET = 0x10 -# default CONFIG_LIFT_BSP_APIC_ID = 0 -# default CONFIG_PCI_64BIT_PREF_MEM = 1 -default CONFIG_IOAPIC = 1 -default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E" -default CONFIG_MAINBOARD_VENDOR = "ASUS" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -# Only use the option table in a normal image. -default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE) -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_GDB_STUB = 0 -default CONFIG_USE_PRINTK_IN_CAR=1 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -default CONFIG_ID_SECTION_OFFSET = 0x80 - -end diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb deleted file mode 100644 index 308a1fecef..0000000000 --- a/src/mainboard/asus/a8v-e_se/Config.lb +++ /dev/null @@ -1,190 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) -## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_ROM_PAYLOAD = 1 - -arch i386 end - -driver mainboard.o -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - mainboardinit southbridge/via/k8t890/romstrap.inc - ldscript /southbridge/via/k8t890/romstrap.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - - mainboardinit cpu/amd/car/cache_as_ram.inc - -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -config chip.h - -chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard (off) - end - device pnp 2e.106 off # Serial flash - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO_PLED - end - device pnp 2e.009 on # GPIO 2 on LDN 9 is in sio_setup - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 on # GPIO5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end - end - end - device pci 12.0 off end # VIA LAN (off, other chip used) - end - chip southbridge/via/k8t890 # "Southbridge" K8T890 - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb deleted file mode 100644 index 92c51feb0c..0000000000 --- a/src/mainboard/asus/a8v-e_se/Options.lb +++ /dev/null @@ -1,165 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License v2 as published by -## the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -# uses CONFIG_USE_OPTION_TABLE -# uses CONFIG_RAMTOP -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -# bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -# bx_b005+ -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_USE_PRINTK_IN_CAR - -default CONFIG_ROM_SIZE = 512 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_GENERATE_PIRQ_TABLE = 0 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME -# Move the default coreboot CMOS range off of AMD RTC registers. -default CONFIG_LB_CKS_RANGE_START = 49 -default CONFIG_LB_CKS_RANGE_END = 122 -default CONFIG_LB_CKS_LOC = 123 -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_MAX_PHYSICAL_CPUS = 1 -default CONFIG_LOGICAL_CPUS = 1 -default CONFIG_GENERATE_ACPI_TABLES = 1 - -# 1G memory hole -# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 - -# Opteron K8 1G HT support -default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 - -# HT Unit ID offset, default is 1, the typical one. -default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 - -# Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 - -# Make the SB HT chain on bus 0, default is not (0). -# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 - -# bx_b005+ make the SB HT chain on bus 0. -default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 - -# Only offset for SB chain?, default is yes(1). -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 - -default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. -default CONFIG_PCI_ROM_RUN = 1 # Needed for VGA. -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xcc000 -default CONFIG_DCACHE_RAM_SIZE = 0x4000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 -default CONFIG_USE_INIT = 0 -default CONFIG_ENABLE_APIC_EXT_ID = 0 -default CONFIG_APIC_ID_OFFSET = 0x10 -default CONFIG_LIFT_BSP_APIC_ID = 0 -default CONFIG_IOAPIC = 1 -default CONFIG_MAINBOARD_VENDOR = "ASUS" -default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 256 * 1024 -# More 1M for pgtbl. -# default CONFIG_RAMTOP = 2048*1024 -default CONFIG_RAMBASE = 0x00004000 -# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_GDB_STUB = 0 -default CONFIG_USE_PRINTK_IN_CAR = 1 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8 -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" -end diff --git a/src/mainboard/asus/m2v-mx_se/Config.lb b/src/mainboard/asus/m2v-mx_se/Config.lb deleted file mode 100644 index 908d1b7309..0000000000 --- a/src/mainboard/asus/m2v-mx_se/Config.lb +++ /dev/null @@ -1,167 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## (Written by Yinghai Lu <yinghailu@amd.com> for AMD) -## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end - -driver mainboard.o -if CONFIG_GENERATE_ACPI_TABLES - object acpi_tables.o - makerule dsdt.c - depends "$(CONFIG_MAINBOARD)/dsdt.asl" - action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl" - action "mv dsdt.hex dsdt.c" - end - object ./dsdt.o -end - - if CONFIG_USE_INIT - makerule ./cache_as_ram_auto.o - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - end - else - makerule ./cache_as_ram_auto.inc - depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" - action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" - action "perl -e 's/\.rodata/.rom.data/g' -pi $@" - action "perl -e 's/\.text/.section .rom.text/g' -pi $@" - end - end - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/entry16.inc - ldscript /cpu/x86/16bit/entry16.lds - mainboardinit southbridge/via/k8t890/romstrap.inc - ldscript /southbridge/via/k8t890/romstrap.lds -end - -mainboardinit cpu/x86/32bit/entry32.inc - - if CONFIG_USE_INIT - ldscript /cpu/x86/32bit/entry32.lds - end - if CONFIG_USE_INIT - ldscript /cpu/amd/car/cache_as_ram.lds - end - -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - - mainboardinit cpu/amd/car/cache_as_ram.inc - -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds -end - - if CONFIG_USE_INIT - initobject cache_as_ram_auto.o - else - mainboardinit ./cache_as_ram_auto.inc - end - -config chip.h - -chip northbridge/amd/amdk8/root_complex # Root complex - device apic_cluster 0 on # APIC cluster - chip cpu/amd/socket_AM2 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0xc0" # Enable SB functions - register "fn_ctrl_hi" = "0x1d" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 0x00 - end - device pnp 2e.5 off end # PS/2 keyboard - device pnp 2e.6 off end # PS/2 mouse - device pnp 2e.7 off end # GPIO config - device pnp 2e.8 off end # Midi port - device pnp 2e.9 off end # Game port - device pnp 2e.a off end # IR - end - end - device pci 12.0 on end # VIA LAN - device pci 13.0 on end # br - device pci 13.1 on end # br2 need to have it here to discover it - end - chip southbridge/via/k8t890 # "Southbridge" K8M890 - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end -end diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb deleted file mode 100644 index eaa7168682..0000000000 --- a/src/mainboard/asus/m2v-mx_se/Options.lb +++ /dev/null @@ -1,174 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License v2 as published by -## the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_MAX_CPUS -uses CONFIG_MAX_PHYSICAL_CPUS -uses CONFIG_LOGICAL_CPUS -uses CONFIG_IOAPIC -uses CONFIG_SMP -uses CONFIG_FALLBACK_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_ROM_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_RAMTOP -uses CONFIG_GENERATE_ACPI_TABLES -uses CONFIG_HAVE_MAINBOARD_RESOURCES -uses CONFIG_HAVE_ACPI_RESUME -uses CONFIG_HAVE_LOW_TABLES -uses CONFIG_LB_CKS_RANGE_START -uses CONFIG_LB_CKS_RANGE_END -uses CONFIG_LB_CKS_LOC -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID -uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses COREBOOT_EXTRA_VERSION -uses CONFIG_RAMBASE -uses CONFIG_GDB_STUB -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_HAVE_INIT_TIMER -uses CONFIG_GDB_STUB -uses CONFIG_VGA -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -# bx_b001- uses K8_HW_MEM_HOLE_SIZEK -uses CONFIG_K8_HT_FREQ_1G_SUPPORT -uses CONFIG_USE_DCACHE_RAM -uses CONFIG_DCACHE_RAM_BASE -uses CONFIG_DCACHE_RAM_SIZE -uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE -uses CONFIG_USE_INIT -uses CONFIG_ENABLE_APIC_EXT_ID -uses CONFIG_APIC_ID_OFFSET -uses CONFIG_LIFT_BSP_APIC_ID -uses CONFIG_HT_CHAIN_UNITID_BASE -uses CONFIG_HT_CHAIN_END_UNITID_BASE -# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -# bx_b005+ -uses CONFIG_SB_HT_CHAIN_ON_BUS0 -uses CONFIG_COMPRESSED_PAYLOAD_NRV2B -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_USE_PRINTK_IN_CAR - -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_HAVE_HARD_RESET = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 0 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_OPTION_TABLE = 1 # FIXME -# Move the default coreboot CMOS range off of AMD RTC registers. -default CONFIG_LB_CKS_RANGE_START = 49 -default CONFIG_LB_CKS_RANGE_END = 122 -default CONFIG_LB_CKS_LOC = 123 -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_MAX_PHYSICAL_CPUS = 1 -default CONFIG_LOGICAL_CPUS = 1 -default CONFIG_GENERATE_ACPI_TABLES = 1 -default CONFIG_HAVE_MAINBOARD_RESOURCES = 1 -default CONFIG_HAVE_LOW_TABLES = 0 -default CONFIG_HAVE_ACPI_RESUME = 1 - -# 1G memory hole -# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000 - -# Opteron K8 1G HT support -default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1 - -# HT Unit ID offset, default is 1, the typical one. -default CONFIG_HT_CHAIN_UNITID_BASE = 0x0 - -# Real SB Unit ID, default is 0x20, mean don't touch it at last. -# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0 - -# Make the SB HT chain on bus 0, default is not (0). -# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2 - -# bx_b005+ make the SB HT chain on bus 0. -default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1 - -# Only offset for SB chain?, default is yes(1). -default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 - -default CONFIG_VGA = 1 -default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. -default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA. -default CONFIG_USE_DCACHE_RAM = 1 -default CONFIG_DCACHE_RAM_BASE = 0xcc000 -default CONFIG_DCACHE_RAM_SIZE = 0x4000 -default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000 -default CONFIG_USE_INIT = 0 -default CONFIG_ENABLE_APIC_EXT_ID = 0 -default CONFIG_APIC_ID_OFFSET = 0x10 -default CONFIG_LIFT_BSP_APIC_ID = 0 -default CONFIG_IOAPIC = 1 -default CONFIG_MAINBOARD_VENDOR = "ASUS" -default CONFIG_MAINBOARD_PART_NUMBER = "M2V-MX SE" -default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 -# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234 # FIXME -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 256 * 1024 -# More 1M for pgtbl. -default CONFIG_RAMTOP = 32768*1024 -# to 1MB -default CONFIG_RAMBASE = 0x1F00000 -default CONFIG_USE_OPTION_TABLE = 0 -# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_ROM_PAYLOAD = 1 -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_GDB_STUB = 0 -default CONFIG_USE_PRINTK_IN_CAR=1 -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON" - -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -end diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb deleted file mode 100644 index af6423c01b..0000000000 --- a/src/mainboard/asus/mew-am/Config.lb +++ /dev/null @@ -1,135 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - # Note: The -mcpu=p2 is important, or else... 'too few registers'. - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -# TODO: On-board graphics. -chip northbridge/intel/i82810 # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # CPU - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) - device pci 1.0 on end # Chipset Graphics Controller (CGC) - chip southbridge/intel/i82801xx # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge - chip superio/smsc/smscsuperio # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 2e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.a on # Power-management events (PME) - io 0x60 = 0x600 - end - device pnp 2e.b on # MIDI port (MPU-401) - io 0x60 = 0x330 - irq 0x70 = 5 - end - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMbus - device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip) - device pci 1f.6 off end # AC'97 modem (N/A) - end - end -end diff --git a/src/mainboard/asus/mew-am/Options.lb b/src/mainboard/asus/mew-am/Options.lb deleted file mode 100644 index c62bf48e49..0000000000 --- a/src/mainboard/asus/mew-am/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 512 * 1024 # Override this in targets/*/Config.lb. -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 8 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 # Override this in targets/*/Config.lb. -default CONFIG_CONSOLE_VGA = 1 # Override this in targets/*/Config.lb. -default CONFIG_PCI_ROM_RUN = 1 # Override this in targets/*/Config.lb. - -end diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb deleted file mode 100644 index 3cd4db2e5f..0000000000 --- a/src/mainboard/asus/mew-vm/Config.lb +++ /dev/null @@ -1,147 +0,0 @@ -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 64 * 1024 -include /config/nofailovercalculation.lb - -## -## Set all of the defaults for an x86 architecture -## - -arch i386 end - -## -## Build the objects we have code for in this directory. -## - -driver mainboard.o - -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end - -## -## Romcc output -## -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end - -makerule ./auto.E - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end - -## -## Build our 16 bit and 32 bit coreboot entry code -## -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds - -## -## Build our reset vector (This is where coreboot is entered) -## -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end - -### Should this be in the northbridge code? -mainboardinit arch/i386/lib/cpu_reset.inc - -## -## Include an id string (For safe flashing) -## -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds - -### -### This is the early phase of coreboot startup -### Things are delicate and we test to see if we should -### failover to another image. -### -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end - -### -### O.k. We aren't just an intermediary anymore! -### - -## -## Setup RAM -## -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -## -## Include the secondary Configuration files -## -dir /pc80 -config chip.h - -chip northbridge/intel/i82810 - device pci_domain 0 on - device pci 0.0 on end # Host bridge - device pci 1.0 on # Onboard Video - # device pci 1.0 on end - end - chip southbridge/intel/i82801xx # Southbridge - register "ide0_enable" = "1" - register "ide1_enable" = "1" - - device pci 1e.0 on # PCI Bridge - # device pci 1.0 on end - end - device pci 1f.0 on # ISA/LPC? Bridge - chip superio/smsc/lpc47b272 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # Keyboard interrupt - irq 0x72 = 12 # Mouse interrupt - end - device pnp 2e.a off end # ACPI - end - end - device pci 1f.1 on end # IDE - device pci 1f.2 on end # USB - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # AC'97, no header on MEW-VM - device pci 1f.6 off end # AC'97 Modem (MC'97) - end - end - chip cpu/intel/socket_PGA370 - end -end - diff --git a/src/mainboard/asus/mew-vm/Options.lb b/src/mainboard/asus/mew-vm/Options.lb deleted file mode 100644 index 50f0b54a7a..0000000000 --- a/src/mainboard/asus/mew-vm/Options.lb +++ /dev/null @@ -1,154 +0,0 @@ -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC - -## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. -default CONFIG_ROM_SIZE = 512*1024 - -### -### Build options -### - -## -## Build code for the fallback boot -## -default CONFIG_HAVE_FALLBACK_BOOT = 1 - -## -## no MP table -## -default CONFIG_GENERATE_MP_TABLE = 0 - -## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET = 0 - -## -## Build code to export a programmable irq routing table -## -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 11 - -## -## Build code to export a CMOS option table -## -default CONFIG_HAVE_OPTION_TABLE = 0 - -### -### coreboot layout values -### - -## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default CONFIG_ROM_IMAGE_SIZE = 65536 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE - -## -## Use a small 8K stack -## -default CONFIG_STACK_SIZE=0x2000 - -## -## Use a small 16K heap -## -default CONFIG_HEAP_SIZE=0x4000 - -## -## Only use the option table in a normal image -## -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 - -default CONFIG_RAMBASE = 0x00004000 - -default CONFIG_ROM_PAYLOAD = 1 - -## -## The default compiler -## -default CONFIG_CROSS_COMPILE="" -default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" - -## -## The Serial Console -## - -# To Enable the Serial Console -default CONFIG_CONSOLE_SERIAL8250=1 - -## Select the serial console baud rate -default CONFIG_TTYS0_BAUD=115200 -#default CONFIG_TTYS0_BAUD=57600 -#default CONFIG_TTYS0_BAUD=38400 -#default CONFIG_TTYS0_BAUD=19200 -#default CONFIG_TTYS0_BAUD=9600 -#default CONFIG_TTYS0_BAUD=4800 -#default CONFIG_TTYS0_BAUD=2400 -#default CONFIG_TTYS0_BAUD=1200 - -# Select the serial console base port -default CONFIG_TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default CONFIG_TTYS0_LCS=0x3 - -## -### Select the coreboot loglevel -## -## EMERG 1 system is unusable -## ALERT 2 action must be taken immediately -## CRIT 3 critical conditions -## ERR 4 error conditions -## WARNING 5 warning conditions -## NOTICE 6 normal but significant condition -## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages -## SPEW 9 Way too many details - -## Request this level of debugging output -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9 -## At a maximum only compile in this level of debugging -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 - -default CONFIG_UDELAY_TSC=1 - -end diff --git a/src/mainboard/asus/p2b-d/Config.lb b/src/mainboard/asus/p2b-d/Config.lb deleted file mode 100644 index 1170d4c091..0000000000 --- a/src/mainboard/asus/p2b-d/Config.lb +++ /dev/null @@ -1,134 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 1 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" - end - end -end diff --git a/src/mainboard/asus/p2b-d/Options.lb b/src/mainboard/asus/p2b-d/Options.lb deleted file mode 100644 index 2ccd3a9d26..0000000000 --- a/src/mainboard/asus/p2b-d/Options.lb +++ /dev/null @@ -1,103 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_SMP -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 6 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_IOAPIC = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 -end diff --git a/src/mainboard/asus/p2b-ds/Config.lb b/src/mainboard/asus/p2b-ds/Config.lb deleted file mode 100644 index 4307c39442..0000000000 --- a/src/mainboard/asus/p2b-ds/Config.lb +++ /dev/null @@ -1,135 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_MP_TABLE object mptable.o end -if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 1 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - device pci 6.0 on end # Onboard SCSI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "1" - register "ide0_drive1_udma33_enable" = "1" - register "ide1_drive0_udma33_enable" = "1" - register "ide1_drive1_udma33_enable" = "1" - end - end -end diff --git a/src/mainboard/asus/p2b-ds/Options.lb b/src/mainboard/asus/p2b-ds/Options.lb deleted file mode 100644 index 45214cf0a3..0000000000 --- a/src/mainboard/asus/p2b-ds/Options.lb +++ /dev/null @@ -1,104 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN -uses CONFIG_SMP -uses CONFIG_MAX_CPUS -uses CONFIG_IOAPIC - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 1 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_SMP = 1 -default CONFIG_MAX_CPUS = 2 -default CONFIG_IOAPIC = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/asus/p2b-f/Config.lb b/src/mainboard/asus/p2b-f/Config.lb deleted file mode 100644 index 4be4b44b6b..0000000000 --- a/src/mainboard/asus/p2b-f/Config.lb +++ /dev/null @@ -1,132 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/asus/p2b-f/Options.lb b/src/mainboard/asus/p2b-f/Options.lb deleted file mode 100644 index 68843932f1..0000000000 --- a/src/mainboard/asus/p2b-f/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 7 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/asus/p2b/Config.lb b/src/mainboard/asus/p2b/Config.lb deleted file mode 100644 index 559694de3c..0000000000 --- a/src/mainboard/asus/p2b/Config.lb +++ /dev/null @@ -1,132 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.9 on # GPIO 3 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/asus/p2b/Options.lb b/src/mainboard/asus/p2b/Options.lb deleted file mode 100644 index 0d1bb91ca8..0000000000 --- a/src/mainboard/asus/p2b/Options.lb +++ /dev/null @@ -1,98 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_PRECOMPRESSED_PAYLOAD -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 6 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end diff --git a/src/mainboard/asus/p3b-f/Config.lb b/src/mainboard/asus/p3b-f/Config.lb deleted file mode 100644 index 628c41372b..0000000000 --- a/src/mainboard/asus/p3b-f/Config.lb +++ /dev/null @@ -1,133 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -## CONFIG_XIP_ROM_SIZE must be a power of 2. -default CONFIG_XIP_ROM_SIZE = 128 * 1024 -include /config/nofailovercalculation.lb -default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1 - -arch i386 end -driver mainboard.o -if CONFIG_GENERATE_PIRQ_TABLE - object irq_tables.o -end -makerule ./failover.E - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./failover.inc - depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" - action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" -end -makerule ./auto.E - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -makerule ./auto.inc - # depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" - depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" - action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" -end -mainboardinit cpu/x86/16bit/entry16.inc -mainboardinit cpu/x86/32bit/entry32.inc -ldscript /cpu/x86/16bit/entry16.lds -ldscript /cpu/x86/32bit/entry32.lds -if CONFIG_USE_FALLBACK_IMAGE - mainboardinit cpu/x86/16bit/reset16.inc - ldscript /cpu/x86/16bit/reset16.lds -else - mainboardinit cpu/x86/32bit/reset32.inc - ldscript /cpu/x86/32bit/reset32.lds -end -mainboardinit arch/i386/lib/cpu_reset.inc -mainboardinit arch/i386/lib/id.inc -ldscript /arch/i386/lib/id.lds -if CONFIG_USE_FALLBACK_IMAGE - ldscript /arch/i386/lib/failover.lds - mainboardinit ./failover.inc -end -mainboardinit cpu/x86/fpu_enable.inc -mainboardinit ./auto.inc -mainboardinit cpu/x86/mmx_disable.inc - -dir /pc80 -config chip.h - -# TODO -chip northbridge/intel/i440bx # Northbridge - device apic_cluster 0 on # APIC cluster - chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually) - device apic 0 on end # APIC - end - end - device pci_domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end -end diff --git a/src/mainboard/asus/p3b-f/Options.lb b/src/mainboard/asus/p3b-f/Options.lb deleted file mode 100644 index 1320c2612d..0000000000 --- a/src/mainboard/asus/p3b-f/Options.lb +++ /dev/null @@ -1,97 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_GENERATE_PIRQ_TABLE -uses CONFIG_USE_FALLBACK_IMAGE -uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET -uses CONFIG_HAVE_OPTION_TABLE -uses CONFIG_USE_OPTION_TABLE -uses CONFIG_ROM_PAYLOAD -uses CONFIG_IRQ_SLOT_COUNT -uses CONFIG_MAINBOARD -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses COREBOOT_EXTRA_VERSION -uses CONFIG_ARCH -uses CONFIG_FALLBACK_SIZE -uses CONFIG_STACK_SIZE -uses CONFIG_HEAP_SIZE -uses CONFIG_ROM_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_IMAGE_SIZE -uses CONFIG_ROM_SECTION_SIZE -uses CONFIG_ROM_SECTION_OFFSET -uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_ROMBASE -uses CONFIG_RAMBASE -uses CONFIG_XIP_ROM_SIZE -uses CONFIG_XIP_ROM_BASE -uses CONFIG_GENERATE_MP_TABLE -uses CONFIG_CROSS_COMPILE -uses CC -uses HOSTCC -uses CONFIG_OBJCOPY -uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses CONFIG_TTYS0_BAUD -uses CONFIG_TTYS0_BASE -uses CONFIG_TTYS0_LCS -uses CONFIG_UDELAY_TSC -uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 -uses CONFIG_MAINBOARD_VENDOR -uses CONFIG_MAINBOARD_PART_NUMBER -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN - -default CONFIG_ROM_SIZE = 256 * 1024 -default CONFIG_HAVE_FALLBACK_BOOT = 1 -default CONFIG_GENERATE_MP_TABLE = 0 -default CONFIG_HAVE_HARD_RESET = 0 -default CONFIG_UDELAY_TSC = 1 -default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 -default CONFIG_GENERATE_PIRQ_TABLE = 1 -default CONFIG_IRQ_SLOT_COUNT = 8 # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_VENDOR = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_MAINBOARD_PART_NUMBER = "N/A" # Override this in targets/*/Config.lb. -default CONFIG_ROM_IMAGE_SIZE = 36 * 1024 -default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE -default CONFIG_STACK_SIZE = 8 * 1024 -default CONFIG_HEAP_SIZE = 16 * 1024 -default CONFIG_HAVE_OPTION_TABLE = 0 -#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE -default CONFIG_USE_OPTION_TABLE = 0 -default CONFIG_RAMBASE = 0x00004000 -default CONFIG_ROM_PAYLOAD = 1 -default CONFIG_CROSS_COMPILE = "" -default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" -default HOSTCC = "gcc" -default CONFIG_CONSOLE_SERIAL8250 = 1 -default CONFIG_TTYS0_BAUD = 115200 -default CONFIG_TTYS0_BASE = 0x3f8 -default CONFIG_TTYS0_LCS = 0x3 # 8n1 -default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 -default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 -default CONFIG_CONSOLE_VGA = 1 -default CONFIG_PCI_ROM_RUN = 1 - -end |