diff options
| author | Rudolf Marek <r.marek@assembler.cz> | 2009-03-21 11:52:29 +0000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2009-03-21 11:52:29 +0000 |
| commit | 4b10ab3782ea30f9832efb297eb0f51eab36d20e (patch) | |
| tree | c6226f875294816a6d166577336c0fed2c37fc93 /src/mainboard/asus | |
| parent | 9e9fa825fdd836f5e13db78ce4dc6bfb182dc35e (diff) | |
To make use of HAVE_HIGH_TABLES following patch is needed. Also, it moves
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a
bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/Options.lb | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb index 74b6917434..47f434eff0 100644 --- a/src/mainboard/asus/m2v-mx_se/Options.lb +++ b/src/mainboard/asus/m2v-mx_se/Options.lb @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> +## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License v2 as published by @@ -44,8 +44,11 @@ uses XIP_ROM_BASE uses STACK_SIZE uses HEAP_SIZE # uses USE_OPTION_TABLE -# uses CONFIG_LB_MEM_TOPK +uses CONFIG_LB_MEM_TOPK uses HAVE_ACPI_TABLES +uses HAVE_MAINBOARD_RESOURCES +uses HAVE_HIGH_TABLES +uses HAVE_LOW_TABLES uses LB_CKS_RANGE_START uses LB_CKS_RANGE_END uses LB_CKS_LOC @@ -110,6 +113,10 @@ default CONFIG_MAX_CPUS = 2 default CONFIG_MAX_PHYSICAL_CPUS = 1 default CONFIG_LOGICAL_CPUS = 1 default HAVE_ACPI_TABLES = 1 +default HAVE_MAINBOARD_RESOURCES = 1 +default HAVE_HIGH_TABLES = 1 +default HAVE_LOW_TABLES = 0 + # default CONFIG_CHIP_NAME = 1 # 1G memory hole @@ -152,8 +159,9 @@ default ROM_IMAGE_SIZE = 64 * 1024 default STACK_SIZE = 8 * 1024 default HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. -# default CONFIG_LB_MEM_TOPK = 2048 -default _RAMBASE = 0x00004000 +default CONFIG_LB_MEM_TOPK = 2048 +# to 1MB +default _RAMBASE = 0x100000 # default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 default CC = "$(CROSS_COMPILE)gcc -m32" |