diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-07-15 18:04:23 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-07-19 15:06:23 +0000 |
| commit | b30a47b841f1c7d55d9cf207e1cc89f1b7f7fa51 (patch) | |
| tree | 26768bd5cafaf5615c4e2e80cee0835308d882d2 /src/mainboard/asus | |
| parent | fa0ef81d155a913b857055c6ce81e628ff866742 (diff) | |
sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supported
The processor P_BLK doesn't support throttling. This behaviour could be
emulated with SMM, but instead just update the FADT to indicate no support
for legacy I/O based throttling using P_CNT.
We have _PTC defined in SSDT, which should be used in favour of P_CNT by
ACPI aware OS, so this change has no effect on modern OS.
Drop all occurences of p_cnt_throttling_supported and update autoport
to not generate it any more.
Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/maximus_iv_gene-z/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/asus/p8h61-m_lx/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/asus/p8h61-m_pro/devicetree.cb | 1 |
3 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 4b80f393f6..0c25d4d91a 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x register "c2_latency" = "101" register "gen1_dec" = "0x00000295" # Super I/O HWM - register "p_cnt_throttling_supported" = "1" register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/asus/p8h61-m_lx/devicetree.cb b/src/mainboard/asus/p8h61-m_lx/devicetree.cb index ef8071fabb..27705b91f7 100644 --- a/src/mainboard/asus/p8h61-m_lx/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_lx/devicetree.cb @@ -40,7 +40,6 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x register "c2_latency" = "101" register "gen1_dec" = "0x00000295" # Super I/O HWM - register "p_cnt_throttling_supported" = "1" register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb index d3f1795f91..e791d70976 100644 --- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -34,7 +34,6 @@ chip northbridge/intel/sandybridge register "c2_latency" = "0x0065" register "docking_supported" = "0" register "gen1_dec" = "0x000c0291" # HWM - register "p_cnt_throttling_supported" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" |