diff options
| author | Idwer Vollering <vidwer@gmail.com> | 2020-01-05 01:44:25 +0100 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-01-09 16:03:07 +0000 |
| commit | c2ce370f30b60daf60e23182cf01eb898d35fbbd (patch) | |
| tree | 7b4fc0f6682a74264c617a26010a8bb1be215a4c /src/mainboard/asus | |
| parent | 7c0711092371a7e92c7b37d252ac4a74992dac87 (diff) | |
src/mainboard: remove MMIO macros
This touches several mainboards. Replace the macro with C functions.
The presence of bootblock.c is assumed.
Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/am1i-a/bootblock.c | 8 | ||||
| -rw-r--r-- | src/mainboard/asus/f2a85-m/bootblock.c | 12 |
2 files changed, 8 insertions, 12 deletions
diff --git a/src/mainboard/asus/am1i-a/bootblock.c b/src/mainboard/asus/am1i-a/bootblock.c index d4017cf282..ddbf2aa548 100644 --- a/src/mainboard/asus/am1i-a/bootblock.c +++ b/src/mainboard/asus/am1i-a/bootblock.c @@ -113,18 +113,16 @@ static void ite_gpio_conf(pnp_devfn_t dev) void bootblock_mainboard_early_init(void) { - volatile u32 i, val, *addr32; + volatile u32 i, val; /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ pm_write8(0xea, 0x1); /* Configure ClkDrvStr1 settings */ - addr32 = (u32 *)0xfed80e24; - *addr32 = 0x030800aa; + misc_write32(0x24, 0x030800aa); /* Configure MiscClkCntl1 settings */ - addr32 = (u32 *)0xfed80e40; - *addr32 = 0x000c4050; + misc_write32(0x40, 0x000c4050); /* Configure SIO as made under vendor BIOS */ ite_gpio_conf(GPIO_DEV); diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c index 648f55a559..0472877dc0 100644 --- a/src/mainboard/asus/f2a85-m/bootblock.c +++ b/src/mainboard/asus/f2a85-m/bootblock.c @@ -16,27 +16,25 @@ #include <bootblock_common.h> #include <device/pnp_type.h> -#include <southbridge/amd/common/amd_defs.h> +#include <amdblocks/acpimmio.h> #include <stdint.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8728f/it8728f.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6779d/nct6779d.h> -#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) - static void sbxxx_enable_48mhzout(void) { /* most likely programming to 48MHz out signal */ u32 reg32; - reg32 = SB_MMIO_MISC32(0x28); + reg32 = misc_read32(0x28); reg32 &= 0xffc7ffff; reg32 |= 0x00100000; - SB_MMIO_MISC32(0x28) = reg32; + misc_write32(0x28, reg32); - reg32 = SB_MMIO_MISC32(0x40); + reg32 = misc_read32(0x40); reg32 &= ~0x80u; - SB_MMIO_MISC32(0x40) = reg32; + misc_write32(0x40, reg32); } static void superio_init_m(void) |