diff options
author | Myles Watson <mylesgw@gmail.com> | 2010-04-08 15:09:53 +0000 |
---|---|---|
committer | Myles Watson <mylesgw@gmail.com> | 2010-04-08 15:09:53 +0000 |
commit | 9b43afde3922e7c4c58dbed85df2a9ea26e11bdf (patch) | |
tree | 68d2f47f5fac45ed545001a376d84085fa46a036 /src/mainboard/asus | |
parent | 4839e2c495d16e7c49acd5eb933ef7f42e67713a (diff) |
Clean up fidvid files using indent.
Remove some special print statements.
In general, make them easier to compare.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r-- | src/mainboard/asus/a8v-e_se/romstage.c | 4 | ||||
-rw-r--r-- | src/mainboard/asus/m2v-mx_se/romstage.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 320f23682c..a2f01b6c52 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -32,10 +32,10 @@ unsigned int get_sbdn(unsigned bus); #define QRANK_DIMM_SUPPORT 1 /* Used by init_cpus and fidvid */ -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 /* If we want to wait for core1 done before DQS training, set it to 0. */ -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #include <stdint.h> #include <string.h> diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 4183ce9b5a..b7313aee2d 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -32,10 +32,10 @@ unsigned int get_sbdn(unsigned bus); #define QRANK_DIMM_SUPPORT 1 /* Used by init_cpus and fidvid */ -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 /* If we want to wait for core1 done before DQS training, set it to 0. */ -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 |