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authorElyes Haouas <ehaouas@noos.fr>2022-11-29 17:36:51 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-12-02 14:39:56 +0000
commitdc3beea75d3050600842112cfd7fd48baa65278d (patch)
treeca9839a61c90cc7b972650c0eb1a2e92a6a25eb9 /src/mainboard/asus
parent87a98b55b2466638587ea44fc7eaa13d93525656 (diff)
sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70114 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r--src/mainboard/asus/p5gc-mx/devicetree.cb4
-rw-r--r--src/mainboard/asus/p5qpl-am/devicetree.cb2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb
index ad9b961dca..a9cad93e33 100644
--- a/src/mainboard/asus/p5gc-mx/devicetree.cb
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -38,8 +38,8 @@ chip northbridge/intel/i945
register "gpe0_en" = "0"
- register "ide_enable_primary" = "0x1"
- register "ide_enable_secondary" = "0x0"
+ register "ide_enable_primary" = "true"
+ register "ide_enable_secondary" = "false"
register "p_cnt_throttling_supported" = "0"
diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb
index 82b1c61078..104485116e 100644
--- a/src/mainboard/asus/p5qpl-am/devicetree.cb
+++ b/src/mainboard/asus/p5qpl-am/devicetree.cb
@@ -29,7 +29,7 @@ chip northbridge/intel/x4x # Northbridge
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
- register "ide_enable_primary" = "0x1"
+ register "ide_enable_primary" = "true"
register "gpe0_en" = "0x04000440"
register "gen1_dec" = "0x00000295" # HWM