diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-01-13 23:41:09 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-01-14 23:25:47 +0000 |
| commit | 85eff9275685b42a7f642e7bd6ba17f33a41e8af (patch) | |
| tree | 5bc32676ba7466362454531d69facf7d13b763dd /src/mainboard/asus | |
| parent | 76f3dbd4335053af7cafe7493abab464c6f90090 (diff) | |
mb/asus/maximus_iv_gene-z: Remove superfluous comments from dt
Since all devicetrees from asus/maximus_iv_gene-z are using the
reference names for PCI devices, remove the equivalent comments
documenting their function.
Change-Id: I86a7d58f34c0cf5580441b7538b1a7571c41c988
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/maximus_iv_gene-z/devicetree.cb | 50 |
1 files changed, 25 insertions, 25 deletions
diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 146ee6c7dc..2642fbd68b 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -5,9 +5,9 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1043 0x844d inherit - device ref host_bridge on end # Host bridge - device ref peg10 on end # PCIe bridge for discrete graphics - device ref igd on end # VGA controller + device ref host_bridge on end + device ref peg10 on end # discrete graphics + device ref igd on end chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00000295" # Super I/O HWM @@ -15,28 +15,28 @@ chip northbridge/intel/sandybridge register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device ref mei1 on end # Management Engine Interface 1 - device ref mei2 off end # Management Engine Interface 2 - device ref me_ide_r off end # Management Engine IDE-R - device ref me_kt off end # Management Engine KT - device ref gbe on # Intel Gigabit Ethernet + device ref mei1 on end + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe on subsystemid 0x1043 0x849c end - device ref ehci2 on end # USB2 EHCI #2 - device ref hda on # HD audio controller + device ref ehci2 on end + device ref hda on subsystemid 0x1043 0x84dc end - device ref pcie_rp1 on end # PCIe port #1 - device ref pcie_rp2 off end # PCIe port #2 - device ref pcie_rp3 off end # PCIe port #3 - device ref pcie_rp4 off end # PCIe port #4 - device ref pcie_rp5 on end # PCIe port #5 - device ref pcie_rp6 on end # PCIe port #6 - device ref pcie_rp7 on end # PCIe port #7 - device ref pcie_rp8 off end # PCIe port #8 - device ref ehci1 on end # USB2 EHCI #1 - device ref pci_bridge off end # PCI bridge - device ref lpc on # LPC bridge + device ref pcie_rp1 on end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp7 on end + device ref pcie_rp8 off end + device ref ehci1 on end + device ref pci_bridge off end + device ref lpc on chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # Parallel @@ -75,10 +75,10 @@ chip northbridge/intel/sandybridge device pnp 2e.17 off end # GPIOA end end - device ref sata1 on end # SATA controller 1 - device ref smbus on end # SMBus - device ref sata2 off end # SATA controller 2 - device ref thermal off end # Thermal + device ref sata1 on end + device ref smbus on end + device ref sata2 off end + device ref thermal off end end end end |