diff options
| author | Joseph Smith <joe@settoplinux.org> | 2009-05-29 13:45:22 +0000 |
|---|---|---|
| committer | Joseph Smith <joe@smittys.pointclark.net> | 2009-05-29 13:45:22 +0000 |
| commit | 60f0f1b18f87332a569ced6c8744a1572517ba39 (patch) | |
| tree | 8a278fad3d544363b676e11800e38365a71b2b11 /src/mainboard/asus | |
| parent | f8a5c6ec02f1e21d62756bda07f755b3a2f4865f (diff) | |
enable/disable IDE 0/1 (Primary/Secondary) interfaces on the i82801xx southbridge.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/mew-am/Config.lb | 5 | ||||
| -rw-r--r-- | src/mainboard/asus/mew-vm/Config.lb | 3 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb index 8756d296b8..e4de52b970 100644 --- a/src/mainboard/asus/mew-am/Config.lb +++ b/src/mainboard/asus/mew-am/Config.lb @@ -82,6 +82,9 @@ chip northbridge/intel/i82810 # Northbridge device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 1.0 on end # Chipset Graphics Controller (CGC) chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1e.0 on end # PCI bridge device pci 1f.0 on # ISA bridge chip superio/smsc/smscsuperio # Super I/O @@ -126,8 +129,6 @@ chip northbridge/intel/i82810 # Northbridge device pci 1f.3 on end # SMbus device pci 1f.5 off end # AC'97 audio (N/A, uses CS4280 chip) device pci 1f.6 off end # AC'97 modem (N/A) - #register "ide0_enable" = "1" - #register "ide1_enable" = "1" end end end diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb index a4a061bbe1..cada58f7ae 100644 --- a/src/mainboard/asus/mew-vm/Config.lb +++ b/src/mainboard/asus/mew-vm/Config.lb @@ -103,6 +103,9 @@ chip northbridge/intel/i82810 #end end chip southbridge/intel/i82801xx # Southbridge + register "ide0_enable" = "1" + register "ide1_enable" = "1" + device pci 1e.0 on # PCI Bridge #chip drivers/pci/onboard # device pci 1.0 on end |