cpu/intel: Enter romstage without BIST

When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.

Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

7 files changed, 8 insertions, 25 deletions

diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c
index 91834cd5f6..a93c0ed2a9 100644
--- a/src/mainboard/asus/p2b-ds/romstage.c
+++ b/src/mainboard/asus/p2b-ds/romstage.c
@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <southbridge/intel/i82371eb/i82371eb.h>
 #include <northbridge/intel/i440bx/raminit.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83977tf/w83977tf.h>
@@ -31,11 +30,10 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
-	report_bist_failure(bist);
 
 	enable_smbus();
 	sdram_initialize();
diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c
index 753f64076e..e77e3dc18d 100644
--- a/src/mainboard/asus/p2b-ls/romstage.c
+++ b/src/mainboard/asus/p2b-ls/romstage.c
@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <southbridge/intel/i82371eb/i82371eb.h>
 #include <northbridge/intel/i440bx/raminit.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/common/winbond.h>
 /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */
@@ -32,11 +31,10 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
-	report_bist_failure(bist);
 
 	enable_smbus();
 	sdram_initialize();
diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c
index 88f61f85b6..b51742907e 100644
--- a/src/mainboard/asus/p2b/romstage.c
+++ b/src/mainboard/asus/p2b/romstage.c
@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <southbridge/intel/i82371eb/i82371eb.h>
 #include <northbridge/intel/i440bx/raminit.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83977tf/w83977tf.h>
@@ -31,11 +30,10 @@ int spd_read_byte(unsigned int device, unsigned int address)
 	return smbus_read_byte(device, address);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
-	report_bist_failure(bist);
 
 	enable_smbus();
 	sdram_initialize();
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
index 387cecb5dd..cc5b764b01 100644
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ b/src/mainboard/asus/p3b-f/romstage.c
@@ -19,7 +19,6 @@
 #include <console/console.h>
 #include <southbridge/intel/i82371eb/i82371eb.h>
 #include <northbridge/intel/i440bx/raminit.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/common/winbond.h>
 /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
@@ -65,11 +64,10 @@ static void disable_spd(void)
 	outb(0x67, PM_IO_BASE + 0x37);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
-	report_bist_failure(bist);
 
 	enable_smbus();
 	enable_pm();
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 4e17d34a85..c3275b5fe1 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -24,7 +24,6 @@
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627dhg/w83627dhg.h>
 #include <console/console.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <northbridge/intel/i945/i945.h>
 #include <northbridge/intel/i945/raminit.h>
@@ -173,14 +172,13 @@ static void early_ich7_init(void)
 	RCBA32(0x2034) = reg32;
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	int s3resume = 0, boot_mode = 0;
 
 	u8 c_bsel = msr_get_fsb();
 
-	if (bist == 0)
-		enable_lapic();
+	enable_lapic();
 
 	ich7_enable_lpc();
 
@@ -189,9 +187,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	/* Set up the console */
 	console_init();
 
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
 	if (MCHBAR16(SSKPD) == 0xCAFE) {
 		printk(BIOS_DEBUG, "soft reset detected.\n");
 		boot_mode = 1;
diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c
index a818b746c7..8af04e3cf9 100644
--- a/src/mainboard/asus/p5qc/romstage.c
+++ b/src/mainboard/asus/p5qc/romstage.c
@@ -20,7 +20,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <northbridge/intel/x4x/x4x.h>
-#include <cpu/x86/bist.h>
 #include <cpu/intel/romstage.h>
 #include <superio/winbond/w83667hg-a/w83667hg-a.h>
 #include <superio/winbond/common/winbond.h>
@@ -66,7 +65,7 @@ static void ich10_enable_lpc(void)
 	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0x001c4701);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
 	u8 boot_path = 0;
@@ -79,7 +78,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	report_bist_failure(bist);
 	enable_smbus();
 
 	x4x_early_init();
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index 7d028434d6..f15a187d94 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -21,7 +21,6 @@
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/intel/speedstep.h>
-#include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <northbridge/intel/x4x/iomap.h>
 #include <northbridge/intel/x4x/x4x.h>
@@ -162,7 +161,7 @@ static void ich7_enable_lpc(void)
 	pci_write_config32(LPC_DEV, 0x84, 0x000295);
 }
 
-void mainboard_romstage_entry(unsigned long bist)
+void mainboard_romstage_entry(void)
 {
 	//                          ch0      ch1
 	const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
@@ -176,7 +175,6 @@ void mainboard_romstage_entry(unsigned long bist)
 
 	console_init();
 
-	report_bist_failure(bist);
 	enable_smbus();
 
 	x4x_early_init();