mb/asus: Add Asus A88XM-E FM2+ with documentation

The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- no optical SPDIF/IO

Successfully booted configurations:
-RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0
-CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland)
-OS:  Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019
-SeaBIOS: 1.12 and 1.13

Known problems:
- IRQ routing is done incorrect way - common problem of fam15h boards
- Windows 7 can't boot because of the incomplete ACPI implementation

Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

27 files changed, 1465 insertions, 0 deletions

diff --git a/src/mainboard/asus/a88xm-e/BiosCallOuts.c b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
new file mode 100644
index 0000000000..24a7208e3b
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/BiosCallOuts.c
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <AGESA.h>
+#include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
+
+#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] = {
+	{AGESA_DO_RESET,                 agesa_Reset },
+	{AGESA_READ_SPD,                 agesa_ReadSpd },
+	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
+	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
+	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
+	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+/**
+ * ASUS A88XM-E board ALC887-VD Verb Table
+ *
+ * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
+ * the vendor BIOS.
+ */
+const CODEC_ENTRY a88xm_e_alc887_VerbTbl[] = {
+	{0x11, 0x90460130},
+	{0x12, 0x40330000},
+	{0x14, 0x01014010},
+	{0x15, 0x411111f0},
+	{0x16, 0x411111f0},
+	{0x17, 0x411111f0},
+	{0x18, 0x01a19040},
+	{0x19, 0x02a19050},
+	{0x1a, 0x0181304f},
+	{0x1b, 0x02214020},
+	{0x1c, 0x411111f0},
+	{0x1d, 0x4044c601},
+	{0x1e, 0x411111f0},
+	{0x1f, 0x411111f0}
+};
+
+static const CODEC_TBL_LIST CodecTableList[] = {
+	{0x10ec0887, (CODEC_ENTRY *)&a88xm_e_alc887_VerbTbl[0]},
+	{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY *)0x0FFFFFFFFUL}
+};
+
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
+{
+	FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
+}
+
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
+{
+	/* Azalia Controller OEM Codec Table Pointer */
+	FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]);
+
+	/* Fan Control */
+	FchParams_env->Imc.ImcEnable = FALSE;
+	FchParams_env->Hwm.HwMonitorEnable = FALSE;
+	FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */
+}
diff --git a/src/mainboard/asus/a88xm-e/Kconfig b/src/mainboard/asus/a88xm-e/Kconfig
new file mode 100644
index 0000000000..6874e9ea90
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_ASUS_A88XM_E
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select CPU_AMD_AGESA_FAMILY15_TN
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+	select SOUTHBRIDGE_AMD_AGESA_HUDSON
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select SUPERIO_ITE_IT8728F
+	select BOARD_ROMSIZE_KB_8192
+	select GFXUMA
+
+config MAINBOARD_DIR
+	string
+	default "asus/a88xm-e"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "A88XM-E"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x200000
+
+config MAX_CPUS
+	int
+	default 4
+
+config HUDSON_XHCI_FWM
+	bool
+	default n
+
+config HUDSON_IMC_FWM
+	bool
+	default n
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config VGA_BIOS_ID
+	string
+	default "1002,990e"
+
+config CONFIG_HUDSON_XHCI_ENABLE
+	bool
+	default n
+
+config HUDSON_LEGACY_FREE
+	bool
+	default n
+
+endif # BOARD_ASUS_A88XM_E
diff --git a/src/mainboard/asus/a88xm-e/Kconfig.name b/src/mainboard/asus/a88xm-e/Kconfig.name
new file mode 100644
index 0000000000..492d6109ee
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_A88XM_E
+	bool "A88XM-E"
diff --git a/src/mainboard/asus/a88xm-e/Makefile.inc b/src/mainboard/asus/a88xm-e/Makefile.inc
new file mode 100644
index 0000000000..549801d78f
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/Makefile.inc
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/a88xm-e/OemCustomize.c b/src/mainboard/asus/a88xm-e/OemCustomize.c
new file mode 100644
index 0000000000..aa880e7bee
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OemCustomize.c
@@ -0,0 +1,158 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <Porting.h>
+#include <AGESA.h>
+
+#include <northbridge/amd/agesa/state_machine.h>
+#include <PlatformMemoryConfiguration.h>
+
+/*
+ * Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
+ *
+ * Lane Id
+ * 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
+ * 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
+ * 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
+ * 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
+ * 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
+ * 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
+ * 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
+ * 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
+ * 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
+ * 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
+ * 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
+ * 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
+ * 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
+ * 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
+ * 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
+ * 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
+ * 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
+ * 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
+ * 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
+ * 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
+ * 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
+ * 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
+ * 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
+ * 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
+ * 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
+ * 25 DP0_TX[P,N]1
+ * 26 DP0_TX[P,N]2
+ * 27 DP0_TX[P,N]3
+ * 28 DP1_TX[P,N]0
+ * 29 DP1_TX[P,N]1
+ * 30 DP1_TX[P,N]2
+ * 31 DP1_TX[P,N]3
+ * 32 DP2_TX[P,N]0
+ * 33 DP2_TX[P,N]1
+ * 34 DP2_TX[P,N]2
+ * 35 DP2_TX[P,N]3
+ * 36 DP2_TX[P,N]4
+ * 37 DP2_TX[P,N]5
+ * 38 DP2_TX[P,N]6
+ */
+
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
+	/* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
+	},
+	/* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 1)
+	},
+	/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
+	{
+		DESCRIPTOR_TERMINATE_LIST,
+		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+		PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
+				HotplugDisabled,
+				PcieGenMaxSupported,
+				PcieGenMaxSupported,
+				AspmDisabled, 0)
+	},
+};
+
+/*
+ * It is not known, if the setup is complete.
+ *
+ * Tested and works: VGA/DVI, HDMI
+ */
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
+	// DP0 to HDMI0/DP
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
+	},
+	// DP1 to FCH
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+	},
+	// DP2 to HDMI1/DP
+	{
+		0,
+		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
+		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
+	},
+};
+
+static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
+	.Flags        = DESCRIPTOR_TERMINATE_LIST,
+	.SocketId     = 0,
+	.PciePortList = PortList,
+	.DdiLinkList  = DdiList,
+};
+
+void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
+{
+	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
+	FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+	FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
+}
+
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
+{
+	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PsppPolicy		= 0;
+}
+
+/*                        CUSTOMER OVERRIDES MEMORY TABLE                                   */
+/*
+ *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ *  use its default conservative settings.
+ */
+
+static CONST PSO_ENTRY ROMDATA MemoryTable_XM_E[] = {
+
+	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
+	NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
+
+	PSO_END
+};
+
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
+{
+	InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_XM_E;
+}
+
+void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
+{
+	/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
+	InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
+}
diff --git a/src/mainboard/asus/a88xm-e/OptionsIds.h b/src/mainboard/asus/a88xm-e/OptionsIds.h
new file mode 100644
index 0000000000..adbb4763ee
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/OptionsIds.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ *    IDSOPT_IDS_ENABLED
+ *    IDSOPT_ERROR_TRAP_ENABLED
+ *    IDSOPT_CONTROL_ENABLED
+ *    IDSOPT_TRACING_ENABLED
+ *    IDSOPT_PERF_ANALYSIS
+ *    IDSOPT_ASSERT_ENABLED
+ *    IDS_DEBUG_PORT
+ *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ **/
+
+//#define IDSOPT_IDS_ENABLED     TRUE
+//#define IDSOPT_CONTROL_ENABLED TRUE
+#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+//#define IDSOPT_PERF_ANALYSIS   TRUE
+#define IDSOPT_ASSERT_ENABLED  TRUE
+//#undef IDSOPT_DEBUG_ENABLED
+//#define IDSOPT_DEBUG_ENABLED  FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW    FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT       FALSE
+//#define IDS_DEBUG_PORT    0x80
+
+#endif
diff --git a/src/mainboard/asus/a88xm-e/acpi/cpstate.asl b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
new file mode 100644
index 0000000000..35583de49f
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/cpstate.asl
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+ */
+
+/*
+ * P-state support: the maximum number of P-states supported
+ * by the CPUs that we'll use - is 6. Taken from AMI BIOS.
+ */
+Name(_PSS, Package(){
+	Package()
+	{
+		0x00000D48,
+		0x00011170,
+		0x00000004,
+		0x00000004,
+		0x00000000,
+		0x00000000
+	},
+
+	Package()
+	{
+		0x00000AF0,
+		0x0000C544,
+		0x00000004,
+		0x00000004,
+		0x00000001,
+		0x00000001
+	},
+
+	Package()
+	{
+		0x000009C4,
+		0x0000B3B0,
+		0x00000004,
+		0x00000004,
+		0x00000002,
+		0x00000002
+	},
+
+	Package()
+	{
+		0x00000898,
+		0x0000ABE0,
+		0x00000004,
+		0x00000004,
+		0x00000003,
+		0x00000003
+	},
+
+	Package()
+	{
+		0x00000708,
+		0x0000A410,
+		0x00000004,
+		0x00000004,
+		0x00000004,
+		0x00000004
+	},
+
+	Package()
+	{
+		0x00000578,
+		0x00006F54,
+		0x00000004,
+		0x00000004,
+		0x00000005,
+		0x00000005
+	}
+})
+
+Name(_PCT, Package(){
+	ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+	ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+})
+
+Method(_PPC, 0){
+	Return(0)
+}
diff --git a/src/mainboard/asus/a88xm-e/acpi/gpe.asl b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
new file mode 100644
index 0000000000..9f01c7a0ca
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/gpe.asl
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+	/* General event 3 */
+	Method(_L03) {
+	}
+
+	/* Legacy PM event */
+	Method(_L08) {
+	}
+
+	/* Temp warning (TWarn) event */
+	Method(_L09) {
+	}
+
+	/* USB controller PME# */
+	Method(_L0B) {
+		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/* ExtEvent0 SCI event */
+	Method(_L10) {
+	}
+
+	/* ExtEvent1 SCI event */
+	Method(_L11) {
+	}
+
+	/* GPIO0 or GEvent8 event */
+	Method(_L18) {
+		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/* Azalia SCI event */
+	Method(_L1B) {
+		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+} /* End Scope GPE */
diff --git a/src/mainboard/asus/a88xm-e/acpi/mainboard.asl b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
new file mode 100644
index 0000000000..699bc6b031
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/mainboard.asl
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+	/* Data to be patched by the BIOS during POST */
+	/* FIXME the patching is not done yet! */
+	/* Memory related values */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	/* Base address of PCIe config space */
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
+	/* Length of PCIe config space, 1MB each bus */
+	Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER))
+	/* Base address of HPET table */
+	Name(HPBA, 0xFED00000)
+
+	/* Some global data */
+	Name(OSVR, 3)   /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones) /* Assume nothing */
+	Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/asus/a88xm-e/acpi/routing.asl b/src/mainboard/asus/a88xm-e/acpi/routing.asl
new file mode 100644
index 0000000000..99511c5a21
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/routing.asl
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+	/* Routing is in System Bus scope */
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - F15 Host Controller */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+		Package(){0x0001FFFF, 0, INTB, 0 },
+		Package(){0x0001FFFF, 1, INTC, 0 },
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+		/* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+		/* Bus 0, Dev 20 -
+		 *        F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB
+		 */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+
+		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */
+		Package(){0x0012FFFF, 0, INTC, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+
+		Package(){0x0016FFFF, 0, INTC, 0 },
+		Package(){0x0016FFFF, 1, INTB, 0 },
+
+		/* SB devices */
+		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+		Package(){0x0010FFFF, 0, INTC, 0 },
+		Package(){0x0010FFFF, 1, INTB, 0 },
+
+		/* Bus 0, Dev 17 - SATA controller */
+		Package(){0x0011FFFF, 0, INTD, 0 },
+
+		/* Bus 0, Dev 21 PCIe Bridge */
+		Package(){0x0015FFFF, 0, INTA, 0 },
+		Package(){0x0015FFFF, 1, INTB, 0 },
+		Package(){0x0015FFFF, 2, INTC, 0 },
+		Package(){0x0015FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - F15 Host Controller */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+		Package(){0x0001FFFF, 0, 0, 17 },
+		Package(){0x0001FFFF, 1, 0, 18 },
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		Package(){0x0002FFFF, 1, 0, 19 },
+		Package(){0x0002FFFF, 2, 0, 16 },
+		Package(){0x0002FFFF, 3, 0, 17 },
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+		/* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		Package(){0x0004FFFF, 1, 0, 17 },
+		Package(){0x0004FFFF, 2, 0, 18 },
+		Package(){0x0004FFFF, 3, 0, 19 },
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+		/* Bus 0, Dev 20 -
+		 *        F0: SMBus/ACPI, F1: IDE, F2: HDAudio, F3: LPC, F4: PCIBridge, F5: USB
+		 */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0, EHCI @ func 2 */
+		Package(){0x0012FFFF, 0, 0, 18 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+
+		Package(){0x0016FFFF, 0, 0, 18 },
+		Package(){0x0016FFFF, 1, 0, 17 },
+
+		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+		Package(){0x0010FFFF, 0, 0, 0x12},
+		Package(){0x0010FFFF, 1, 0, 0x11},
+
+		/* Bus 0, Dev 17 - SATA controller */
+		Package(){0x0011FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 21 PCIE Bridge */
+		Package(){0x0015FFFF, 0, 0, 17 },
+		Package(){0x0015FFFF, 1, 0, 18 },
+		Package(){0x0015FFFF, 2, 0, 19 },
+		Package(){0x0015FFFF, 3, 0, 16 },
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	/* black slot */
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PBR0, Package(){
+		/* PCIx1 on SB */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+	Name(ABR0, Package(){
+		/* PCIx1 on SB */
+		Package(){0x0000FFFF, 0, 0, 0x10 },
+		Package(){0x0000FFFF, 1, 0, 0x11 },
+		Package(){0x0000FFFF, 2, 0, 0x12 },
+		Package(){0x0000FFFF, 3, 0, 0x13 },
+	})
+
+	Name(PBR1, Package(){
+		/* Onboard network */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+	Name(ABR1, Package(){
+		/* Onboard network */
+		Package(){0x0000FFFF, 0, 0, 0x11 },
+		Package(){0x0000FFFF, 1, 0, 0x12 },
+		Package(){0x0000FFFF, 2, 0, 0x13 },
+		Package(){0x0000FFFF, 3, 0, 0x10 },
+	})
+
+	/* SB PCI Bridge  */
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+	})
diff --git a/src/mainboard/asus/a88xm-e/acpi/sata.asl b/src/mainboard/asus/a88xm-e/acpi/sata.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sata.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/si.asl b/src/mainboard/asus/a88xm-e/acpi/si.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/si.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/sleep.asl b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
new file mode 100644
index 0000000000..87773378c9
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/sleep.asl
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+ * \_PTS - Prepare to Sleep method
+ *
+ *	Entry:
+ *		Arg0=The value of the sleeping state S1=1, S2=2, etc
+ *
+ * Exit:
+ *		-none-
+ *
+ * The _PTS control method is executed at the beginning of the sleep process
+ * for S1-S5. The sleeping value is passed to the _PTS control method.  This
+ * control method may be executed a relatively long time before entering the
+ * sleep state and the OS may abort the operation without notification to
+ * the ACPI driver.  This method cannot modify the configuration or power
+ * state of any device in the system.
+ */
+Method(\_PTS, 1) {
+
+	/* Clear wake status structure. */
+	Store(0, Index(WKST,0))
+	Store(0, Index(WKST,1))
+
+	Store (0x07, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+ *  \_WAK System Wake method
+ *
+ *	Entry:
+ *		Arg0=The value of the sleeping state S1=1, S2=2
+ *
+ *	Exit:
+ *		Return package of 2 DWords
+ *		Dword 1 - Status
+ *			0x00000000	wake succeeded
+ *			0x00000001	Wake was signaled but failed due to lack of power
+ *			0x00000002	Wake was signaled but failed due to thermal condition
+ *		Dword 2 - Power Supply state
+ *			if non-zero the effective S-state the power supply entered
+ */
+Method(\_WAK, 1) {
+	Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/a88xm-e/acpi/superio.asl b/src/mainboard/asus/a88xm-e/acpi/superio.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/superio.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/thermal.asl b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/thermal.asl
diff --git a/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
new file mode 100644
index 0000000000..d90fffdd40
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi/usb_oc.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/asus/a88xm-e/acpi_tables.c b/src/mainboard/asus/a88xm-e/acpi_tables.c
new file mode 100644
index 0000000000..ff4a3b97b6
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/acpi_tables.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <arch/ioapic.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write Hudson IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+					   IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edge-triggered, Active high */
+
+	/* create all subtables for processors */
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
diff --git a/src/mainboard/asus/a88xm-e/board_info.txt b/src/mainboard/asus/a88xm-e/board_info.txt
new file mode 100644
index 0000000000..579dce634d
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/Motherboards/A88XME/
+ROM package: DIP8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y (without AmdSpiRomProtect modules)
+Release year: 2014
diff --git a/src/mainboard/asus/a88xm-e/bootblock.c b/src/mainboard/asus/a88xm-e/bootblock.c
new file mode 100644
index 0000000000..0bc8d2e15e
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/bootblock.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpimmio.h>
+#include <bootblock_common.h>
+#include <device/pnp_type.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+static void sbxxx_enable_48mhzout(void)
+{
+	/* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
+	u32 reg32;
+	reg32 = misc_read32(0x28);
+	reg32 &= ~(7 << 19);
+	reg32 |=  (2 << 19);
+	misc_write32(0x28, reg32);
+
+	/* Enable Auxiliary OSCOUT2 */
+	misc_write32(0x40, misc_read32(0x40) & ~(1 << 7));
+}
+
+static void superio_init_m(void)
+{
+	const pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
+	const pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
+
+	ite_kill_watchdog(gpio);
+	ite_enable_serial(uart, CONFIG_TTYS0_BASE);
+	ite_enable_3vsbsw(gpio);
+}
+
+void bootblock_mainboard_early_init(void)
+{
+	/* enable SIO clock */
+	sbxxx_enable_48mhzout();
+
+	superio_init_m();
+}
diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c
new file mode 100644
index 0000000000..76fafca604
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/buildOpts.c
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <vendorcode/amd/agesa/f15tn/AGESA.h>
+
+/* Include the files that instantiate the configuration definitions. */
+#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
+/* AGESA nonsense: the next two headers depend on heapManager.h */
+#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
+/* These tables are optional and may be used to adjust memory timing settings */
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
+#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
+
+/* Select the CPU family */
+#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT	TRUE
+
+/* Select the CPU socket type */
+#define INSTALL_FM2_SOCKET_SUPPORT		TRUE
+
+#define BLDOPT_REMOVE_SODIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_LRDIMMS_SUPPORT		TRUE
+#define BLDOPT_REMOVE_ECC_SUPPORT		TRUE
+#define BLDOPT_REMOVE_SRAT			FALSE
+#define BLDOPT_REMOVE_WHEA			FALSE
+#define	BLDOPT_REMOVE_CRAT			TRUE
+
+/* Build configuration values here. */
+#define BLDCFG_AMD_PLATFORM_TYPE		AMD_PLATFORM_DESKTOP
+
+#define BLDCFG_MEMORY_RDIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE		TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE		FALSE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING	TRUE
+#define BLDCFG_MEMORY_CLOCK_SELECT		DDR1866_FREQUENCY
+#define BLDCFG_ENABLE_ECC_FEATURE		FALSE
+#define BLDCFG_ECC_SYNC_FLOOD			FALSE
+
+#define BLDCFG_PLATFORM_CPB_MODE		CpbModeAuto
+
+#define BLDCFG_UMA_ALLOCATION_MODE		UMA_SPECIFIED
+#define BLDCFG_UMA_ALLOCATION_SIZE		0x2000 /* (0x2000 << 16) = 512M */
+
+#define BLDCFG_IOMMU_SUPPORT			TRUE
+
+#define BLDCFG_CFG_GNB_HD_AUDIO			TRUE
+
+/* Customized OEM build configurations for FCH component */
+#define BLDCFG_FCH_GPP_LINK_CONFIG		PortA1B1C1D1
+#define BLDCFG_FCH_GPP_PORT0_PRESENT		TRUE
+#define BLDCFG_FCH_GPP_PORT1_PRESENT		TRUE
+#define BLDCFG_FCH_GPP_PORT2_PRESENT		TRUE
+
+GPIO_CONTROL a88xm_e_gpio[] = {
+	{-1}
+};
+#define BLDCFG_FCH_GPIO_CONTROL_LIST		(a88xm_e_gpio)
+
+/* Moving this include up will break AGESA. */
+#include <PlatformInstall.h>
diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout
new file mode 100644
index 0000000000..2355292411
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/cmos.layout
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+388          4       h       0        reboot_counter
+#392          3       r       0        unused
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+#456          1       e       1        ECC_memory
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+6     0     Emergency
+6     1     Alert
+6     2     Critical
+6     3     Error
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/a88xm-e/devicetree.cb b/src/mainboard/asus/a88xm-e/devicetree.cb
new file mode 100644
index 0000000000..f427d0d88b
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/devicetree.cb
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/amd/agesa/family15tn/root_complex
+
+	device cpu_cluster 0 on
+		chip cpu/amd/agesa/family15tn
+			device lapic 10 on end
+		end
+	end
+
+	device domain 0 on
+		subsystemid 0x1022 0x1410 inherit
+		chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+			chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+				device pci 0.0 on  end # Root Complex
+				device pci 0.2 on  end # IOMMU
+				device pci 1.0 on  end # Internal Graphics P2P bridge 0x99XX
+				device pci 1.1 on  end # Internal Multimedia (iGPU Audio)
+				device pci 2.0 on  end # PCIEX16
+				device pci 3.0 off end # -
+				device pci 4.0 off end # PCIe x4 (?)
+				device pci 5.0 off end # PCIe x1 (?)
+				device pci 6.0 off end # PCIe x1 (?)
+				device pci 7.0 off end # PCIe x1 (?)
+				device pci 8.0 off end # NB/SB Link P2P bridge
+			end	#chip northbridge/amd/agesa/family15tn
+
+			chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+				device pci 10.0 on  end # XHCI HC0
+				device pci 10.1 on  end # XHCI HC1
+				device pci 11.0 on  end # SATA AHCI
+				device pci 12.0 on  end # USB OHCI
+				device pci 12.2 on  end # USB EHCI
+				device pci 13.0 on  end # USB OHCI
+				device pci 13.2 on  end # USB EHCI
+				device pci 14.0 on  end # SMBUS
+				device pci 14.1 off end # IDE
+				device pci 14.2 on  end # HDA
+				device pci 14.3 on      # LPC
+					chip superio/ite/it8728f
+						register "TMPIN1.mode" = "THERMAL_RESISTOR"
+						register "TMPIN2.mode" = "THERMAL_RESISTOR"
+						register "TMPIN3.mode" = "THERMAL_RESISTOR"
+
+						register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+						register "FAN1.smart.tmpin" = "1"
+						register "FAN1.smart.tmp_off" = "0x80" # never
+						register "FAN1.smart.tmp_start" = "20"
+						register "FAN1.smart.tmp_full" = "70"
+						register "FAN1.smart.tmp_delta" = "0"
+						register "FAN1.smart.smoothing" = "1"
+						register "FAN1.smart.pwm_start" = "20"
+						register "FAN1.smart.slope" = "32"
+
+						# Enable tacho reading for chassis fan.
+						register "FAN2.mode" = "FAN_MODE_OFF"
+
+						device pnp 2e.0 off end # Floppy
+						device pnp 2e.1 on # COM1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.2 off end # COM2
+						device pnp 2e.3 off end # Parallel Port
+						device pnp 2e.4 on # Env Controller
+							io 0x60 = 0x290
+							io 0x62 = 0x220
+							irq 0x70 = 0
+						end
+						device pnp 2e.5 on # Keyboard
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1
+						end
+						device pnp 2e.6 on # Mouse
+							irq 0x70 = 12
+						end
+						device pnp 2e.7 on # GPIO
+							io 0x60 = 0x228 # SMI
+							io 0x62 = 0x300 # Simple I/O
+							io 0x64 = 0 # Phony resource IT8603E does not have it
+							irq 0x70 = 0
+						end
+						device pnp 2e.a off end #  CIR
+					end	#superio/ite/it8728f
+				end	#device pci 14.3 # LPC
+				device pci 14.4 on  end # PCI bridge
+				device pci 14.5 on  end # USB OHCI
+				device pci 14.6 off end # Gec
+				device pci 14.7 off end # SD
+				device pci 15.0 on  end # PCIe RP0: PCIEX1_1
+				device pci 15.1 off end # PCIe RP1: -
+				device pci 15.2 on  end # PCIe RP2: Onboard Ethernet
+				device pci 15.3 off end # PCIe RP3: -
+			end	#chip southbridge/amd/agesa/hudson
+
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+
+			register "spdAddrLookup" = "
+			{
+				/* socket 0 - Channel 0 & 1 - 8-bit SPD addresses */
+				{ {0xA0, 0x00}, {0xA2, 0x00}, },
+			}"
+
+		end	#chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+	end	#domain
+end	#chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/a88xm-e/dsdt.asl b/src/mainboard/asus/a88xm-e/dsdt.asl
new file mode 100644
index 0000000000..aac9c84cd5
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/dsdt.asl
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* DefinitionBlock Statement */
+#include <acpi/acpi.h>
+DefinitionBlock (
+	"DSDT.AML",		/* Output filename */
+	"DSDT",			/* Signature */
+	0x02,			/* DSDT Revision, needs to be 2 for 64bit */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x00010001		/* OEM Revision */
+	)
+{	/* Start of ASL file */
+
+	/* Globals for the platform */
+	#include "acpi/mainboard.asl"
+
+	/* Describe the USB Overcurrent pins */
+	#include "acpi/usb_oc.asl"
+
+	/* PCI IRQ mapping for the Southbridge */
+	#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>
+
+	/* Describe the processor tree (\_PR) */
+	#include <cpu/amd/agesa/family15tn/acpi/cpu.asl>
+
+	/* Describe the supported Sleep States for this Southbridge */
+	#include <southbridge/amd/common/acpi/sleepstates.asl>
+
+	/* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
+	#include "acpi/sleep.asl"
+
+	Scope(\_SB) {
+		/* global utility methods expected within the \_SB scope */
+		#include <arch/x86/acpi/globutil.asl>
+
+		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+		#include "acpi/routing.asl"
+
+		Device(PCI0) {
+			/* Describe the AMD Northbridge */
+			#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>
+
+			/* Describe the AMD Fusion Controller Hub Southbridge */
+			#include <southbridge/amd/agesa/hudson/acpi/fch.asl>
+		}
+
+		/* Describe PCI INT[A-H] for the Southbridge */
+		#include <southbridge/amd/agesa/hudson/acpi/pci_int.asl>
+
+	}   /* End Scope(_SB)  */
+
+	/* Describe SMBUS for the Southbridge */
+	#include <southbridge/amd/agesa/hudson/acpi/smbus.asl>
+
+	/* Define the General Purpose Events for the platform */
+	#include "acpi/gpe.asl"
+
+	/* Define the Thermal zones and methods for the platform */
+	#include "acpi/thermal.asl"
+
+	/* Define the System Indicators for the platform */
+	#include "acpi/si.asl"
+
+}
+/* End of ASL file */
diff --git a/src/mainboard/asus/a88xm-e/irq_tables.c b/src/mainboard/asus/a88xm-e/irq_tables.c
new file mode 100644
index 0000000000..7ca1c4b951
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/irq_tables.c
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <string.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+
+	u8 sum = 0;
+	int i;
+
+	/* Align the table to be 16 byte aligned. */
+	addr = ALIGN_UP(addr, 16);
+
+	/* This table must be between 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = 0;
+	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->slots);
+	slot_num = 0;
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	pirq_info++;
+
+	slot_num++;
+
+	pirq->size = 32 + 16 * slot_num;
+
+	{
+		const u8 *const v = (u8 *)(pirq);
+		for (i = 0; i < pirq->size; i++)
+			sum += v[i];
+	}
+
+	sum = pirq->checksum - sum;
+
+	if (sum != pirq->checksum)
+		pirq->checksum = sum;
+
+	printk(BIOS_INFO, "%s done.\n", __func__);
+
+	return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/asus/a88xm-e/mainboard.c b/src/mainboard/asus/a88xm-e/mainboard.c
new file mode 100644
index 0000000000..2e08188d15
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mainboard.c
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
+#include <device/device.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+static const u8 mainboard_picr_data[] = {
+	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0A, 0xF1, 0x00, 0x00, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
+};
+static const u8 mainboard_intr_data[84] = {
+	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F,
+	0x1F, 0x1F, 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x13, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x11, 0x12, 0x13,
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+	intr_data_ptr = mainboard_intr_data;
+	picr_data_ptr = mainboard_picr_data;
+}
+
+/* dedicated "enable" function (taken from thatcher) */
+static void mainboard_enable(struct device *dev)
+{
+	msr_t msr;
+
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+	pirq_setup();
+
+	msr = rdmsr(LS_CFG_MSR);
+	/* Enable streaming store functionality. */
+	msr.lo &= ~(1 << 28);
+	wrmsr(LS_CFG_MSR, msr);
+
+	msr = rdmsr(DC_CFG_MSR);
+	/* Enable speculative TLB preloads. */
+	msr.lo &= ~(1 << 4);
+	/* Enable the DC hardware prefetcher. */
+	msr.lo &= ~(1 << 13);
+	wrmsr(DC_CFG_MSR, msr);
+
+	msr = rdmsr(BU_CFG_MSR);
+	/* Disable the L2 way lock. */
+	msr.lo &= ~(1 << 23);
+	wrmsr(BU_CFG_MSR, msr);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/a88xm-e/mptable.c b/src/mainboard/asus/a88xm-e/mptable.c
new file mode 100644
index 0000000000..b9e743c5f3
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/mptable.c
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <string.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
+{
+	mc->mpc_length += length;
+	mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+			     unsigned char id, const char *bustype)
+{
+	struct mpc_config_bus *mpc;
+	mpc = smp_next_mpc_entry(mc);
+	memset(mpc, '\0', sizeof(*mpc));
+	mpc->mpc_type = MP_BUS;
+	mpc->mpc_busid = id;
+	memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+	smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	int bus_isa;
+
+	/*
+	 * By the time this function gets called, the IOAPIC registers
+	 * have been written so they can be read to get the correct
+	 * APIC ID and Version
+	 */
+	u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+	u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LOCAL_APIC_ADDR);
+	memcpy(mc->mpc_oem, "AMD     ", 8);
+
+	smp_write_processors(mc);
+
+	//mptable_write_buses(mc, NULL, &bus_isa);
+	my_smp_write_bus(mc, 0, "PCI   ");
+	my_smp_write_bus(mc, 1, "PCI   ");
+	bus_isa = 0x02;
+	my_smp_write_bus(mc, bus_isa, "ISA   ");
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin)				\
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,\
+	bus_isa, (intr), (apicid), (pin))
+	mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#define PCI_INT(bus, dev, int_sign, pin)				\
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
+	(bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+	/* IOMMU */
+	PCI_INT(0x0, 0x0, 0x0, 0x10);
+	PCI_INT(0x0, 0x0, 0x1, 0x11);
+	PCI_INT(0x0, 0x0, 0x2, 0x12);
+	PCI_INT(0x0, 0x0, 0x3, 0x13);
+
+	/* Internal VGA */
+	PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]);
+
+	/* SMBUS */
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+	/* HD Audio */
+	PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]);
+
+	/* USB */
+	PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]);
+	PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]);
+	PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]);
+	PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]);
+
+	/* on board NIC & Slot PCIE.  */
+
+	/* PCI slots */
+	struct device *dev = pcidev_on_root(0x14, 4);
+	if (dev && dev->enabled) {
+		u8 bus_pci = dev->link_list->secondary;
+		/* PCI_SLOT 0. */
+		PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+		PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+		PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+		PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+	}
+
+	/* PCIe Lan */
+	PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+	/* FCH PCIe PortA */
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
+	/* FCH PCIe PortB */
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
+	/* FCH PCIe PortC */
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
+	/* FCH PCIe PortD */
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+	/* Local Ints:   Type   IRQ   APIC ID   PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/a88xm-e/romstage.c b/src/mainboard/asus/a88xm-e/romstage.c
new file mode 100644
index 0000000000..c9ba041d03
--- /dev/null
+++ b/src/mainboard/asus/a88xm-e/romstage.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpimmio.h>
+#include <arch/io.h>
+#include <northbridge/amd/agesa/state_machine.h>
+#include <southbridge/amd/agesa/hudson/smbus.h>
+
+static void smbus_setup(void)
+{
+	post_code(0x30);
+
+	/* turn on secondary smbus at b20 */
+	pm_write8(0x28, pm_read8(0x28) | 0x01);
+}
+
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+	smbus_setup();
+}