mb/asus/p8z77-v_lx2: Transform into variant setup

Get ready to squash all Asus Z77 boards together, so as to factor out
some redundant code.

Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8Z77-V LX2
remains identical when not adding the .config file in it.

Change-Id: I701ec4adbc65732ffc0a60d311bf07bf7f414ebf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

9 files changed, 519 insertions, 0 deletions

diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/board_info.txt b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/board_info.txt
new file mode 100644
index 0000000000..79c36d6837
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asus.com/uk/Motherboards/P8Z77V_LX2/
+ROM package: DIP-8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year: 2013
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/cmos.default b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/cmos.default
new file mode 100644
index 0000000000..c7aa6208f4
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=64M
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/cmos.layout b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/cmos.layout
new file mode 100644
index 0000000000..0f9de5ed18
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/cmos.layout
@@ -0,0 +1,86 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+
+409	2	e	4	power_on_after_fail
+411	2	e	5	sata_mode
+
+# coreboot config options: northbridge
+416	5	e	6	gfx_uma_size
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID	value	text
+
+# Generic on/off enum
+1	0	Disable
+1	1	Enable
+
+# boot_option
+2	0	Fallback
+2	1	Normal
+
+# debug_level
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+# power_on_after_fail
+4	0	Disable
+4	1	Enable
+4	2	Keep
+
+# sata_mode
+5	0	AHCI
+5	1	Compatible
+5	2	Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+6	0	32M
+6	1	64M
+6	2	96M
+6	3	128M
+6	4	160M
+6	5	192M
+6	6	224M
+6	7	256M
+6	8	288M
+6	9	320M
+6	10	352M
+6	11	384M
+6	12	416M
+6	13	448M
+6	14	480M
+6	15	512M
+6	16	1024M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/data.vbt b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/data.vbt
new file mode 100644
index 0000000000..f8151e1678
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/data.vbt
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/devicetree.cb
new file mode 100644
index 0000000000..40f8e6db2b
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/devicetree.cb
@@ -0,0 +1,97 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	device cpu_cluster 0 on
+		chip cpu/intel/model_206ax
+			register "acpi_c1" = "1"
+			register "acpi_c2" = "3"
+			register "acpi_c3" = "5"
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
+	end
+	device domain 0 on
+		subsystemid 0x1043 0x84ca inherit
+		device pci 00.0 on  end		# Host bridge
+		device pci 01.0 on  end		# PCIEX16_1
+		device pci 02.0 on  end		# iGPU
+
+		chip southbridge/intel/bd82x6x
+			register "c2_latency" = "0x0065"
+			register "gen1_dec" = "0x000c0291"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x3f"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+			register "superspeed_capable_ports" = "0x0000000f"
+			register "xhci_overcurrent_mapping" = "0x00000c03"
+			register "xhci_switchable_ports"    = "0x0000000f"
+
+			device pci 14.0 on  end		# xHCI
+			device pci 16.0 on  end		# MEI #1
+			device pci 16.1 off end		# MEI #2
+			device pci 16.2 off end		# ME IDE-R
+			device pci 16.3 off end		# ME KT
+			device pci 19.0 off end		# Intel GbE
+			device pci 1a.0 on  end		# EHCI #2
+			device pci 1b.0 on  end		# HD Audio
+
+			device pci 1c.0 on  end		# RP #1: PCIEX16_2 (electrical x4)
+			device pci 1c.1 off end		# RP #2:
+			device pci 1c.2 off end		# RP #3:
+			device pci 1c.3 off end		# RP #4:
+			device pci 1c.4 on  end		# RP #5: RTL8111 GbE NIC
+			device pci 1c.5 on  end		# RP #6: ASM1083 PCI Bridge
+			device pci 1c.6 on  end		# RP #7: PCIEX1_1
+			device pci 1c.7 on  end		# RP #8: PCIEX1_2
+
+			device pci 1d.0 on  end		# EHCI #1
+			device pci 1e.0 off end		# PCI bridge
+			device pci 1f.0 on		# LPC bridge
+				chip superio/nuvoton/nct6779d
+					device pnp 2e.1   off end	# Parallel
+					device pnp 2e.2   on		# UART A
+						io  0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3   off end	# UART B, IR
+					device pnp 2e.5   on		# Keyboard
+						io  0x60 = 0x0060
+						io  0x62 = 0x0064
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6   off end	# CIR
+					device pnp 2e.7   off end	# GPIO6-8
+					device pnp 2e.8   off end	# WDT1, GPIO0, GPIO1
+					device pnp 2e.108 off end	# GPIO0
+					device pnp 2e.9   off end	# GPIO8
+					device pnp 2e.109 off end	# GPIO1
+					device pnp 2e.209 on		# GPIO2
+						irq 0xe0 = 0xff
+					end
+					device pnp 2e.309 off end	# GPIO3
+					device pnp 2e.409 off end	# GPIO4
+					device pnp 2e.509 off end	# GPIO5
+					device pnp 2e.609 off end	# GPIO6
+					device pnp 2e.709 off end	# GPIO7
+					device pnp 2e.a   on  end	# ACPI
+					device pnp 2e.b   on		# H/W Monitor, FP LED
+						io  0x60 = 0x0290
+						io  0x62 = 0
+						irq 0x70 = 0
+					end
+					device pnp 2e.d   off end	# WDT1
+					device pnp 2e.e   off end	# CIR Wake-up
+					device pnp 2e.f   off end	# Push-pull/Open-drain
+					device pnp 2e.14  off end	# Port 80 UART
+					device pnp 2e.16  off end	# Deep Sleep
+				end
+			end
+			device pci 1f.2 on  end		# SATA (AHCI)
+			device pci 1f.3 on  end		# SMBus
+			device pci 1f.5 off end		# SATA (Legacy)
+			device pci 1f.6 off end		# Thermal
+		end
+	end
+end
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/early_init.c
new file mode 100644
index 0000000000..3a297f9e38
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/early_init.c
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pnp_ops.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+#define ACPI_DEV   PNP_DEV(0x2e, NCT6779D_ACPI)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },
+	{ 1, 0, 0 },
+	{ 1, 0, 1 },
+	{ 1, 0, 1 },
+	{ 1, 0, 2 },
+	{ 1, 0, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 0, 4 },
+	{ 1, 0, 4 },
+	{ 1, 0, 6 },
+	{ 1, 0, 5 },
+	{ 1, 0, 5 },
+	{ 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Select SIO pin states */
+	pnp_write_config(GLOBAL_DEV, 0x1a, 0x02);
+	pnp_write_config(GLOBAL_DEV, 0x1b, 0x70);
+	pnp_write_config(GLOBAL_DEV, 0x1c, 0x10);
+	pnp_write_config(GLOBAL_DEV, 0x1d, 0x0e);
+	pnp_write_config(GLOBAL_DEV, 0x22, 0xd7);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x48);
+	pnp_write_config(GLOBAL_DEV, 0x2c, 0x00);
+
+	/* Power RAM in S3 */
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	/* Enable UART */
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[1], 0x51, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+	read_spd(&spd[3], 0x53, id_only);
+}
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/gma-mainboard.ads b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/gma-mainboard.ads
new file mode 100644
index 0000000000..aa8a70d156
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/gma-mainboard.ads
@@ -0,0 +1,16 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI3,
+      Analog,
+      Others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/gpio.c b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/gpio.c
new file mode 100644
index 0000000000..9e59cd8b56
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/gpio.c
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio11 = GPIO_MODE_GPIO,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_GPIO,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_GPIO,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio28 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_GPIO,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_GPIO,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_GPIO,
+	.gpio62 = GPIO_MODE_GPIO,
+	.gpio63 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio44 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio58 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_INPUT,
+	.gpio61 = GPIO_DIR_INPUT,
+	.gpio62 = GPIO_DIR_INPUT,
+	.gpio63 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,
+	.gpio65 = GPIO_MODE_GPIO,
+	.gpio66 = GPIO_MODE_GPIO,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio65 = GPIO_DIR_INPUT,
+	.gpio66 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+	.gpio75 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/hda_verb.c b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/hda_verb.c
new file mode 100644
index 0000000000..650cd7c990
--- /dev/null
+++ b/src/mainboard/asus/p8z77-series/variants/p8z77-v_lx2/hda_verb.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0887,	/* Codec Vendor / Device ID: Realtek ALC887 */
+	0x10438445,	/* Subsystem ID */
+	15,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x10438445),
+	AZALIA_PIN_CFG(0, 0x11, 0x99430130),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19c50),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4004c601),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+	0x80862806,	/* Codec Vendor / Device ID: Intel HDMI */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x58560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;