diff options
| author | Keith Hui <buurin@gmail.com> | 2024-02-05 19:18:43 -0500 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-06-08 00:19:23 +0000 |
| commit | a911b758482025d46e132eeb2ed0279b65692075 (patch) | |
| tree | fb8475ef03a0365132fefb82bc248468ef0a4784 /src/mainboard/asus/p8x7x-series/devicetree.cb | |
| parent | ee126348726b24fbf6e5435bb2cf15417959a8f7 (diff) | |
mb/*: Remove old USB configurations from SNB/bd82x6x boards
Remove USB configurations and data structures from northbridge
devicetree (SNB+MRC boards) and bootblock/romstage C code
(native-only SNB boards). All USB configurations are drawn from
southbridge devicetree going forward.
Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p8x7x-series/devicetree.cb')
| -rw-r--r-- | src/mainboard/asus/p8x7x-series/devicetree.cb | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index 4052cf43ad..e9b97bc7ba 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -7,11 +7,6 @@ chip northbridge/intel/sandybridge register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" - register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} - }" # 4 bit switch mask. 0=not switchable, 1=switchable # Means once it's loaded the OS, it can swap ports # from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf |