mb/asus/p8h61-m_pro: Add new mainboard

Tested with GRUB 2.02 as a payload, booting Arch Linux as
well as Debian. This code is based on the output of autoport
as well as other mainboards supported in coreboot already.

Working:
 - Serial port I/O
 - S3 suspend/resume. Untested with SeaBIOS since it failed
   to resume on a similar board. It is likely to be due to
   low memory corruption, but I have not worked on it.
 - USB ports and headers
 - USB3 ports attached to the ASM1042 controller. SeaBIOS can
   boot from them, and it is likely GRUB can detect devices on
   those ports as well. The chip has a small SPI flash nearby,
   which seems to hold an Option ROM.
 - Gigabit Ethernet
 - Integrated graphics (libgfxinit)
 - VGA BIOS for integrated graphics init
 - PCIe x16 graphics
 - PCIe x1
 - SATA controller
 - Hardware Monitor
 - Fan Control (fancontrol on linux works well)
 - Native raminit
 - flashrom, using the internal programmer. Tested with coreboot,
   as well as with the vendor firmware.
 - NVRAM settings. Only debug_level has been tested.

Untested:
 - DVI port. It can detect a "fake" display, that is, an
   EEPROM connected to the DVI port. Thus, gma-mainboard.ads
   has been setup accordingly.
 - PS/2 port.
 - Audio: Only rear output (green) has been tested.
 - EHCI debug.
 - Parallel port header.
 - Non-Linux OSes
 - ACPI thermal zone and fan control (probably not working)

Not working:
 - Booting from devices attached to the ASM1061 controller.
   Devices on ports work fine once Linux has loaded.
 - Any SATA devices with Tianocore (payload issue)

Change-Id: I7e89ebe43a2e1ff0308f4876e98bbf2f5a0d85f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/26419
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 86 insertions, 0 deletions

diff --git a/src/mainboard/asus/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/p8h61-m_pro/hda_verb.c
new file mode 100644
index 0000000000..13b25ed438
--- /dev/null
+++ b/src/mainboard/asus/p8h61-m_pro/hda_verb.c
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0887, /* Codec Vendor / Device ID: Realtek */
+	0x10438444, /* Subsystem ID */
+
+	0x0000000f, /* Number of 4 dword sets */
+	/* NID 0x01: Subsystem ID.  */
+	AZALIA_SUBVENDOR(0x0, 0x10438444),
+
+	/* NID 0x11.  */
+	AZALIA_PIN_CFG(0x0, 0x11, 0x99430140),
+
+	/* NID 0x12.  */
+	AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
+
+	/* NID 0x14.  */
+	AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),
+
+	/* NID 0x15.  */
+	AZALIA_PIN_CFG(0x0, 0x15, 0x01011012),
+
+	/* NID 0x16.  */
+	AZALIA_PIN_CFG(0x0, 0x16, 0x01016011),
+
+	/* NID 0x17.  */
+	AZALIA_PIN_CFG(0x0, 0x17, 0x01012014),
+
+	/* NID 0x18.  */
+	AZALIA_PIN_CFG(0x0, 0x18, 0x01a19850),
+
+	/* NID 0x19.  */
+	AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c60),
+
+	/* NID 0x1a.  */
+	AZALIA_PIN_CFG(0x0, 0x1a, 0x0181305f),
+
+	/* NID 0x1b.  */
+	AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20),
+
+	/* NID 0x1c.  */
+	AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
+
+	/* NID 0x1d.  */
+	AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601),
+
+	/* NID 0x1e.  */
+	AZALIA_PIN_CFG(0x0, 0x1e, 0x01456130),
+
+	/* NID 0x1f.  */
+	AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),
+	0x80862805, /* Codec Vendor / Device ID: Intel */
+	0x80860101, /* Subsystem ID */
+
+	0x00000004, /* Number of 4 dword sets */
+	/* NID 0x01: Subsystem ID.  */
+	AZALIA_SUBVENDOR(0x3, 0x80860101),
+
+	/* NID 0x05.  */
+	AZALIA_PIN_CFG(0x3, 0x05, 0x58560010),
+
+	/* NID 0x06.  */
+	AZALIA_PIN_CFG(0x3, 0x06, 0x58560020),
+
+	/* NID 0x07.  */
+	AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;