mb/asus/p8h61-m_lx3_r2_0: Add new mainboard

This is a micro ATX board with a LGA1155 socket and two DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.
Actually, I have the PLUS variant, but they use the same PCB. The only
difference is the capacitor quality.

Working:
 - Both DIMM slots
 - PS/2 keyboard
 - S3 suspend/resume
 - Rear USB ports
 - Integrated graphics (libgfxinit)
 - VGA
 - All PCIe ports
 - Realtek GbE (coreboot must set the MAC address)
 - SATA ports
 - Native raminit
 - Flashing with flashrom
 - Rear audio output
 - VBT
 - Arch Linux using CorebootPayloadPkg

Untested:
 - PS/2 mouse
 - The other audio jacks
 - EHCI debug
 - Front USB headers
 - Non-Linux OSes

Change-Id: I385ee72673202d896041209ff2911995307cb6af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

1 files changed, 89 insertions, 0 deletions

diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb
new file mode 100644
index 0000000000..6d919592eb
--- /dev/null
+++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/devicetree.cb
@@ -0,0 +1,89 @@
+## SPDX-License-Identifier: GPL-2.0-only
+## This file is part of the coreboot project.
+
+chip northbridge/intel/sandybridge
+	device cpu_cluster 0 on
+		chip cpu/intel/model_206ax
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
+	end
+	device domain 0 on
+		subsystemid 0x1043 0x844d inherit
+		device pci 00.0 on end		# Host bridge
+		device pci 01.0 on end		# PEG
+		device pci 02.0 on end		# iGPU
+
+		chip southbridge/intel/bd82x6x
+			register "c2_latency" = "0x0065"
+			register "gen1_dec" = "0x000c0291"
+			register "sata_port_map" = "0x3f"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+
+			device pci 16.0 on  end		# MEI #1
+			device pci 16.1 off end		# MEI #2
+			device pci 16.2 off end		# ME IDE-R
+			device pci 16.3 off end		# ME KT
+			device pci 19.0 off end		# Intel GbE
+			device pci 1a.0 on  end		# USB2 EHCI #2
+			device pci 1b.0 on  end		# HD Audio
+
+			device pci 1c.0 on  end		# RP #1
+			device pci 1c.1 off end		# RP #2
+			device pci 1c.2 off end		# RP #3
+			device pci 1c.3 on  end		# RP #4: PCIEX1_1
+			device pci 1c.4 on  end		# RP #5: PCIEX1_2
+			device pci 1c.5 on  end		# RP #6: RTL8111 GbE NIC
+
+			device pci 1d.0 on  end		# USB2 EHCI #1
+			device pci 1e.0 off end		# PCI bridge
+			device pci 1f.0 on		# LPC bridge
+				chip superio/nuvoton/nct6779d
+					device pnp 2e.1   off end	# Parallel
+					device pnp 2e.2   off end	# UART A
+					device pnp 2e.3   off end	# UART B, IR
+					device pnp 2e.5   on		# Keyboard
+						io  0x60 = 0x0060
+						io  0x62 = 0x0064
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6   off end	# CIR
+					device pnp 2e.7   off end	# GPIO6-8
+					device pnp 2e.8   off end	# WDT1, GPIO0, GPIO1
+					device pnp 2e.108 on  end	# GPIO0
+					device pnp 2e.9   off end	# GPIO1-8
+					device pnp 2e.109 off end	# GPIO1
+					device pnp 2e.209 off end	# GPIO2
+					device pnp 2e.309 off end	# GPIO3
+					device pnp 2e.409 off end	# GPIO4
+					device pnp 2e.509 on  end	# GPIO5
+					device pnp 2e.609 off end	# GPIO6
+					device pnp 2e.709 off end	# GPIO7
+					device pnp 2e.a   on  end	# ACPI
+					device pnp 2e.b   on		# H/W Monitor, FP LED
+						io  0x60 = 0x0290
+						io  0x62 = 0
+						irq 0x70 = 0
+					end
+					device pnp 2e.d   off end	# WDT1
+					device pnp 2e.e   off end	# CIR WAKE-UP
+					device pnp 2e.f   off end	# Push-pull/Open-drain
+					device pnp 2e.14  off end	# PORT80 UART
+					device pnp 2e.16  off end	# Deep Sleep
+				end
+			end
+			device pci 1f.2 on  end		# SATA (AHCI)
+			device pci 1f.3 on  end		# SMBus
+			device pci 1f.5 off end		# SATA (Legacy)
+			device pci 1f.6 off end		# Thermal
+		end
+	end
+end