diff options
author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 19:11:50 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:48:35 +0000 |
commit | fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 (patch) | |
tree | af8d33b500b91fa9e2f1a76d9115086644ccf3d2 /src/mainboard/asus/p8h61-m_lx/romstage.c | |
parent | 59eb2fdb6b06618311ef118996ca8c1d28a85ffc (diff) |
nb/intel/sandybridge: Set up console in bootblock
Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/asus/p8h61-m_lx/romstage.c')
-rw-r--r-- | src/mainboard/asus/p8h61-m_lx/romstage.c | 59 |
1 files changed, 0 insertions, 59 deletions
diff --git a/src/mainboard/asus/p8h61-m_lx/romstage.c b/src/mainboard/asus/p8h61-m_lx/romstage.c deleted file mode 100644 index d3361919a7..0000000000 --- a/src/mainboard/asus/p8h61-m_lx/romstage.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi> - * - * This program is free software: you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/pci_ops.h> -#include <device/dram/ddr3.h> -#include <northbridge/intel/sandybridge/raminit_native.h> -#include <northbridge/intel/sandybridge/sandybridge.h> -#include <southbridge/intel/bd82x6x/pch.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6776/nct6776.h> - -#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - -void mainboard_pch_lpc_setup(void) -{ - pci_or_config16(PCH_LPC_DEV, LPC_EN, - CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); -} - -void mainboard_config_superio(void) -{ - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} |