aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/asus/p5qc/hda_verb.c
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-07-18 11:48:47 +0200
committerFelix Held <felix-coreboot@felixheld.de>2018-10-15 14:10:18 +0000
commit1541256f22bbb046a43ccebf73d994d4f4a53374 (patch)
treef3fbbf0a870b5462b51e9347c91550146f54db13 /src/mainboard/asus/p5qc/hda_verb.c
parent6db1b2fc24e5634d139d34c93813c2f703583494 (diff)
mb/asus/p5qc: Add mainboard
SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS support for ATA. It works fine in Linux afterwards. Working: - SATA on southbridge port - SATA on marvel IDE controller ports (only in Linux) - USB - COM1 - PS2 Keyboard - DDR2 DIMMs - PCIe x16 PEG port - PCI port - NIC (needs a driver to set macaddress) - S3 resume Not working: - SeaBIOS with ATA support (long timeout marvel controller so disabled) - DDR3 fails because the proper clock signal does not get enabled. Even when fixing this it fails later or during memtest, so it should be considered unsupported for now Untested: - PCIe x1 ports (expected to work) - sound (expected to work) TODO: add documentation Change-Id: I4a81940707566776bd048904ca1387fea741fece Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asus/p5qc/hda_verb.c')
-rw-r--r--src/mainboard/asus/p5qc/hda_verb.c45
1 files changed, 45 insertions, 0 deletions
diff --git a/src/mainboard/asus/p5qc/hda_verb.c b/src/mainboard/asus/p5qc/hda_verb.c
new file mode 100644
index 0000000000..22832bbb19
--- /dev/null
+++ b/src/mainboard/asus/p5qc/hda_verb.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0888,
+ 0x104382fe, // Subsystem ID
+ 13, // Number of entries
+
+ /* Pin Widget Verb Table */
+
+ AZALIA_PIN_CFG(0, 0x11, 0x99430140),
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+ AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+ AZALIA_PIN_CFG(0, 0x17, 0x01012014),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19d60),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181305f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214d20),
+ AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4015e601),
+ AZALIA_PIN_CFG(0, 0x1e, 0x01447130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);
+const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);