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| author | Subrata Banik <subratabanik@google.com> | 2022-06-05 18:57:36 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-14 17:57:51 +0000 |
| commit | 13fd3c8daef57b9b7728f5145a4241f4ee15c72f (patch) | |
| tree | 9e32d9366ace75a0c8901073ef87af936d5b983b /src/mainboard/asus/p5qc/cmos.layout | |
| parent | 91bc6d1da79b0c48d39770be84cdb2b2afde3050 (diff) | |
soc/intel/cmn/cpu: API to initialize core PRMRR
This patch implements API to sync between core
PRMRR(Processor Reserved Memory Range Registers).
Read PRMRR base and limit value from BSP and apply it on the
rest of the cores.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I720669139429afc3d8c8d15c0ce15f1524f22e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Diffstat (limited to 'src/mainboard/asus/p5qc/cmos.layout')
0 files changed, 0 insertions, 0 deletions