mb/asus/p5qc: Add mainboard

SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS
support for ATA. It works fine in Linux afterwards.

Working:
- SATA on southbridge port
- SATA on marvel IDE controller ports (only in Linux)
- USB
- COM1
- PS2 Keyboard
- DDR2 DIMMs
- PCIe x16 PEG port
- PCI port
- NIC (needs a driver to set macaddress)
- S3 resume

Not working:
- SeaBIOS with ATA support (long timeout marvel controller so disabled)
- DDR3 fails because the proper clock signal does not get enabled. Even when
fixing this it fails later or during memtest, so it should be considered
unsupported for now

Untested:
- PCIe x1 ports (expected to work)
- sound (expected to work)

TODO:
add documentation

Change-Id: I4a81940707566776bd048904ca1387fea741fece
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

4 files changed, 89 insertions, 0 deletions

diff --git a/src/mainboard/asus/p5qc/acpi/ec.asl b/src/mainboard/asus/p5qc/acpi/ec.asl
new file mode 100644
index 0000000000..2997587d82
--- /dev/null
+++ b/src/mainboard/asus/p5qc/acpi/ec.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl
new file mode 100644
index 0000000000..e8cb26eb65
--- /dev/null
+++ b/src/mainboard/asus/p5qc/acpi/ich10_pci_irqs.asl
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
+ */
+
+If (PICM) {
+	Return (Package() {
+		/* PCI slot */
+		Package() { 0x0000ffff, 0, 0, 0x10},
+		Package() { 0x0000ffff, 1, 0, 0x11},
+		Package() { 0x0000ffff, 2, 0, 0x12},
+		Package() { 0x0000ffff, 3, 0, 0x13},
+
+		Package() { 0x0001ffff, 0, 0, 0x11},
+		Package() { 0x0001ffff, 1, 0, 0x12},
+		Package() { 0x0001ffff, 2, 0, 0x13},
+		Package() { 0x0001ffff, 3, 0, 0x10},
+
+		Package() { 0x0002ffff, 0, 0, 0x12},
+		Package() { 0x0002ffff, 1, 0, 0x13},
+		Package() { 0x0002ffff, 2, 0, 0x10},
+		Package() { 0x0002ffff, 3, 0, 0x11},
+
+		Package() { 0x0003ffff, 0, 0, 0x13},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},
+
+		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+	})
+}
diff --git a/src/mainboard/asus/p5qc/acpi/platform.asl b/src/mainboard/asus/p5qc/acpi/platform.asl
new file mode 100644
index 0000000000..6c92a4ed47
--- /dev/null
+++ b/src/mainboard/asus/p5qc/acpi/platform.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Method(_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice.  */
+	Store(Arg0, PICM)
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	/* SMI Function */
+	Store (0, TRP0)		/* Generate trap */
+	Return (SMIF)		/* Return value of SMI handler */
+}
diff --git a/src/mainboard/asus/p5qc/acpi/superio.asl b/src/mainboard/asus/p5qc/acpi/superio.asl
new file mode 100644
index 0000000000..8f414f586f
--- /dev/null
+++ b/src/mainboard/asus/p5qc/acpi/superio.asl
@@ -0,0 +1 @@
+/* TODO */